Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753196AbbBSR0V (ORCPT ); Thu, 19 Feb 2015 12:26:21 -0500 Received: from mail-by2on0086.outbound.protection.outlook.com ([207.46.100.86]:4384 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752889AbbBSR0T (ORCPT ); Thu, 19 Feb 2015 12:26:19 -0500 From: To: CC: , , , , , Dinh Nguyen Subject: [RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller Date: Thu, 19 Feb 2015 11:06:46 -0600 Message-ID: <1424365606-19964-2-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1424365606-19964-1-git-send-email-dinguyen@opensource.altera.com> References: <1424365606-19964-1-git-send-email-dinguyen@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BN1PR08CA0014.namprd08.prod.outlook.com (10.242.217.142) To BY1PR0301MB1192.namprd03.prod.outlook.com (25.160.195.150) Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=dinguyen@opensource.altera.com; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1192; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005003);SRVR:BY1PR0301MB1192; X-Forefront-PRVS: 0492FD61DD X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(6009001)(199003)(189002)(46102003)(33646002)(86362001)(122386002)(53416004)(40100003)(42186005)(76176999)(50986999)(86152002)(62966003)(87976001)(101416001)(97736003)(77156002)(2950100001)(68736005)(69596002)(19580405001)(19580395003)(92566002)(48376002)(50466002)(105586002)(2351001)(47776003)(64706001)(81156004)(110136001)(66066001)(106356001)(229853001)(50226001)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BY1PR0301MB1192;H:linux-builds1.altera.com;FPR:;SPF:None;PTR:InfoNoRecords;A:0;MX:1;LANG:en; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1192; X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2015 17:11:57.4597 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1192 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1485 Lines: 39 From: Dinh Nguyen By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index a5f1fda..4ce2100 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -105,7 +105,8 @@ static const char *altera_dt_match[] = { DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH | - L310_AUX_CTRL_INSTR_PREFETCH, + L310_AUX_CTRL_INSTR_PREFETCH | + L2C_AUX_CTRL_SHARED_OVERRIDE, .l2c_aux_mask = ~0, .smp = smp_ops(socfpga_smp_ops), .map_io = socfpga_map_io, -- 2.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/