Message-ID: <54E61FFF.2010201@intel.com>
Date: Thu, 19 Feb 2015 19:40:15 +0200
From: Adrian Hunter <adrian.hunter@intel.com>
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To: John Stultz <john.stultz@linaro.org>
CC: Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        lkml <linux-kernel@vger.kernel.org>, David Ahern <dsahern@gmail.com>,
        Frederic Weisbecker <fweisbec@gmail.com>, Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@gmail.com>, Paul Mackerras <paulus@samba.org>,
        Stephane Eranian <eranian@google.com>,
        Thomas Gleixner <tglx@linutronix.de>, Pawel Moll <pawel.moll@arm.com>,
        Steven Rostedt <rostedt@goodmis.org>, Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 0/2] perf/x86: Add ability to sample TSC
References: <1424347870-8492-1-git-send-email-adrian.hunter@intel.com> <CALAqxLVDfGhim1+iO=_mXmrpc6vWGmjFJGCRBx39rM0RXobr+Q@mail.gmail.com>
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On 19/02/2015 7:24 p.m., John Stultz wrote:
> On Thu, Feb 19, 2015 at 4:11 AM, Adrian Hunter <adrian.hunter@intel.com> wrote:
>> Hi
>>
>> With the advent of switching perf_clock to CLOCK_MONOTONIC,
>> it will not be possible to convert perf_clock directly to/from
>> TSC. So add the ability to sample TSC instead.
>>
>>
>> Adrian Hunter (2):
>>        perf: Sample additional clock value
>>        perf/x86: Provide TSC for PERF_SAMPLE_CLOCK_ARCH
>
> This doesn't seem very portable. The CLOCK_MONOTONIC_RAW clockid was
> added to provide a arch-neutral abstraction of a free-running hardware
> counter that isn't affected by adjtimex slewing (though like any
> counter, it will be affected by non-constant drift).
>
> You might consider looking at that if the short term slew adjustments
> (which result in more accurate timings in the long term) are
> problematic for you.

This is for Intel Processor Trace - which Peter has already
rightly chastised me for not making plain.

Intel Processor Trace (Intel PT) is a trace that is hardware generated. The
hardware does not know about linux or its clocks, so the timestamps
are TSC. I think ARM might have the same issue with ETM or such. i.e. the
need to synchronize a hardware timestamp with a perf event.

There is a description of Intel PT in the Intel Architecture manuals.

http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

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