Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752750AbbBSRuX (ORCPT ); Thu, 19 Feb 2015 12:50:23 -0500 Received: from mail-ig0-f174.google.com ([209.85.213.174]:62235 "EHLO mail-ig0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751595AbbBSRuW (ORCPT ); Thu, 19 Feb 2015 12:50:22 -0500 MIME-Version: 1.0 In-Reply-To: <54E61FFF.2010201@intel.com> References: <1424347870-8492-1-git-send-email-adrian.hunter@intel.com> <54E61FFF.2010201@intel.com> Date: Thu, 19 Feb 2015 09:50:21 -0800 Message-ID: Subject: Re: [PATCH 0/2] perf/x86: Add ability to sample TSC From: John Stultz To: Adrian Hunter Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , lkml , David Ahern , Frederic Weisbecker , Jiri Olsa , Namhyung Kim , Paul Mackerras , Stephane Eranian , Thomas Gleixner , Pawel Moll , Steven Rostedt , Andi Kleen , Mathieu Poirier Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1901 Lines: 49 On Thu, Feb 19, 2015 at 9:40 AM, Adrian Hunter wrote: > On 19/02/2015 7:24 p.m., John Stultz wrote: >> >> On Thu, Feb 19, 2015 at 4:11 AM, Adrian Hunter >> wrote: >>> >>> Hi >>> >>> With the advent of switching perf_clock to CLOCK_MONOTONIC, >>> it will not be possible to convert perf_clock directly to/from >>> TSC. So add the ability to sample TSC instead. >>> >>> >>> Adrian Hunter (2): >>> perf: Sample additional clock value >>> perf/x86: Provide TSC for PERF_SAMPLE_CLOCK_ARCH >> >> >> This doesn't seem very portable. The CLOCK_MONOTONIC_RAW clockid was >> added to provide a arch-neutral abstraction of a free-running hardware >> counter that isn't affected by adjtimex slewing (though like any >> counter, it will be affected by non-constant drift). >> >> You might consider looking at that if the short term slew adjustments >> (which result in more accurate timings in the long term) are >> problematic for you. > > > This is for Intel Processor Trace - which Peter has already > rightly chastised me for not making plain. > > Intel Processor Trace (Intel PT) is a trace that is hardware generated. The > hardware does not know about linux or its clocks, so the timestamps > are TSC. I think ARM might have the same issue with ETM or such. i.e. the > need to synchronize a hardware timestamp with a perf event. > > There is a description of Intel PT in the Intel Architecture manuals. > > http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Cc'ing Mathieu since he might be familiar w/ any similar issues w/ Coresight. thanks -john -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/