Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753198AbbBWWxF (ORCPT ); Mon, 23 Feb 2015 17:53:05 -0500 Received: from mail-ie0-f172.google.com ([209.85.223.172]:40871 "EHLO mail-ie0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752028AbbBWWxD (ORCPT ); Mon, 23 Feb 2015 17:53:03 -0500 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: linux-kernel@vger.kernel.org, Leonid Yegoshin , Markos Chandras , David Daney Subject: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction" Date: Mon, 23 Feb 2015 14:52:54 -0800 Message-Id: <1424731974-27926-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1800 Lines: 60 From: David Daney This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed. There are two problems: 1) It breaks OCTEON, which will now crash in early boot with: Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80) 2) The logic is broken. The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction is required. The offending patch attempts (and fails) to change the meaning to be that EHB is part of the ISA. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index d75ff73..ff8d99c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -501,7 +501,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case tlb_indexed: tlbw = uasm_i_tlbwi; break; } - if (cpu_has_mips_r2_exec_hazard) { + if (cpu_has_mips_r2) { /* * The architecture spec says an ehb is required here, * but a number of cores do not have the hazard and @@ -1953,7 +1953,7 @@ static void build_r4000_tlb_load_handler(void) switch (current_cpu_type()) { default: - if (cpu_has_mips_r2_exec_hazard) { + if (cpu_has_mips_r2) { uasm_i_ehb(&p); case CPU_CAVIUM_OCTEON: @@ -2020,7 +2020,7 @@ static void build_r4000_tlb_load_handler(void) switch (current_cpu_type()) { default: - if (cpu_has_mips_r2_exec_hazard) { + if (cpu_has_mips_r2) { uasm_i_ehb(&p); case CPU_CAVIUM_OCTEON: -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/