Message-ID: <54EC02D3.6060906@codeaurora.org>
Date: Tue, 24 Feb 2015 10:19:23 +0530
From: Archit Taneja <architt@codeaurora.org>
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To: Georgi Djakov <georgi.djakov@linaro.org>, sboyd@codeaurora.org,
        mturquette@linaro.org
CC: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
References: <1423249118-22132-1-git-send-email-georgi.djakov@linaro.org>
In-Reply-To: <1423249118-22132-1-git-send-email-georgi.djakov@linaro.org>
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Hi,

On 02/07/2015 12:28 AM, Georgi Djakov wrote:
> This is preliminary and not fully tested patch which adds
> support for the global clock controller found on the MSM8916
> based devices. It allows the various device drivers to probe
> and control their clocks and resets.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

<snip>

> +
> +static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
> +	{ .src = P_DSI0_PHYPLL_BYTE },
> +	{ }
> +};
> +
> +static struct clk_rcg2 byte0_clk_src = {
> +	.cmd_rcgr = 0x4d094,

This should be 0x4d044. The one above corresponds to the byte0_cbcr 
register.

> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0a_dsibyte_map,
> +	.freq_tbl = ftbl_gcc_mdss_byte0_clk,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "byte0_clk_src",
> +		.parent_names = gcc_xo_gpll0a_dsibyte,
> +		.num_parents = 2,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
> +	F(19200000, P_XO, 1, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 esc0_clk_src = {
> +	.cmd_rcgr = 0x4d05c,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_dsibyte_map,
> +	.freq_tbl = ftbl_gcc_mdss_esc0_clk,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "esc0_clk_src",
> +		.parent_names = gcc_xo_dsibyte,
> +		.num_parents = 2,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
> +	F(50000000, P_GPLL0, 16, 0, 0),
> +	F(80000000, P_GPLL0, 10, 0, 0),
> +	F(100000000, P_GPLL0, 8, 0, 0),
> +	F(160000000, P_GPLL0, 5, 0, 0),
> +	F(177780000, P_GPLL0, 4.5, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	F(266670000, P_GPLL0, 3, 0, 0),
> +	F(320000000, P_GPLL0, 2.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 mdp_clk_src = {
> +	.cmd_rcgr = 0x4d014,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_dsiphy_map,
> +	.freq_tbl = ftbl_gcc_mdss_mdp_clk,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "mdp_clk_src",
> +		.parent_names = gcc_xo_gpll0_dsiphy,
> +		.num_parents = 1,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
> +	{ .src = P_DSI0_PHYPLL_DSI },
> +	{ }
> +};
> +
> +static struct clk_rcg2 pclk0_clk_src = {
> +	.cmd_rcgr = 0x4d084,

This should be 0x4d000. Same reason as above.

> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_dsiphy_map,
> +	.freq_tbl = ftbl_gcc_mdss_pclk,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "pclk0_clk_src",
> +		.parent_names = gcc_xo_gpll0_dsiphy,
> +		.num_parents = 1,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
> +	F(19200000, P_XO, 1, 0,	0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 vsync_clk_src = {
> +	.cmd_rcgr = 0x4d02c,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0a_map,
> +	.freq_tbl = ftbl_gcc_mdss_vsync_clk,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "vsync_clk_src",
> +		.parent_names = gcc_xo_gpll0a,
> +		.num_parents = 2,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +

mdss clocks look fine otherwise.

Thanks,
Archit

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