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From: Rob Herring <robherring2@gmail.com>
Date: Tue, 24 Feb 2015 08:42:37 -0600
Message-ID: <CAL_JsqKkVHaf_U0nU9nqa2q5XwfsuCu-ZWVEHx6b5Mv9Hgen1Q@mail.gmail.com>
Subject: Re: [PATCH] ARM64: Add new Xilinx ZynqMP SoC
To: Michal Simek <michal.simek@xilinx.com>
Cc: "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will.deacon@arm.com>, Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>,
        =?UTF-8?Q?S=C3=B6ren_Brinkmann?= <soren.brinkmann@xilinx.com>,
        Robert Richter <rrichter@cavium.com>, Mark Brown <broonie@linaro.org>,
        Eddie Huang <eddie.huang@mediatek.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
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On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> Initial version of device tree for Xilinx ZynqMP SoC.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
> ---

[...]

> +               gic: interrupt-controller@f9010000 {
> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

gic-400, right?

> +                       #interrupt-cells = <3>;
> +                       reg = <0x0 0xf9010000 0x10000>,
> +                             <0x0 0xf9020000 0x20000>,
> +                             <0x0 0xf9040000 0x20000>,
> +                             <0x0 0xf9060000 0x20000>;

These addresses are wrong if you are doing address swizzling to do 64K
offsets. We don't really have an answer yet as to what is the right
way. See the XGene GIC discussion[1].

Rob

[1] https://www.mail-archive.com/devicetree@vger.kernel.org/msg62547.html
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