Message-ID: <54EC9D83.1000900@linaro.org>
Date: Tue, 24 Feb 2015 17:49:23 +0200
From: Georgi Djakov <georgi.djakov@linaro.org>
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To: Archit Taneja <architt@codeaurora.org>, sboyd@codeaurora.org,
        mturquette@linaro.org
CC: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
References: <1423249118-22132-1-git-send-email-georgi.djakov@linaro.org> <54EC02D3.6060906@codeaurora.org>
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On 02/24/2015 06:49 AM, Archit Taneja wrote:
> Hi,
[..]
>> +
>> +static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
>> +    { .src = P_DSI0_PHYPLL_DSI },
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 pclk0_clk_src = {
>> +    .cmd_rcgr = 0x4d084,
> 
> This should be 0x4d000. Same reason as above.
> 
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_xo_gpll0_dsiphy_map,
>> +    .freq_tbl = ftbl_gcc_mdss_pclk,
>> +    .clkr.hw.init = &(struct clk_init_data){
>> +        .name = "pclk0_clk_src",
>> +        .parent_names = gcc_xo_gpll0_dsiphy,
>> +        .num_parents = 1,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
>> +    F(19200000, P_XO, 1, 0,    0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 vsync_clk_src = {
>> +    .cmd_rcgr = 0x4d02c,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_xo_gpll0a_map,
>> +    .freq_tbl = ftbl_gcc_mdss_vsync_clk,
>> +    .clkr.hw.init = &(struct clk_init_data){
>> +        .name = "vsync_clk_src",
>> +        .parent_names = gcc_xo_gpll0a,
>> +        .num_parents = 2,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
> 
> mdss clocks look fine otherwise.
> 
> Thanks,
> Archit
> 

Hi Archit,
Thanks for taking a look. I have fixed these and also a few more.

BR,
Georgi

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