From: Vikas Shivappa <vikas.shivappa@linux.intel.com>
To: linux-kernel@vger.kernel.org
Cc: vikas.shivappa@intel.com, vikas.shivappa@linux.intel.com,
        matt.fleming@intel.com, hpa@zytor.com, tglx@linutronix.de,
        mingo@kernel.org, tj@kernel.org, peterz@infradead.org,
        will.auld@intel.com, dave.hansen@intel.com, andi.kleen@intel.com,
        tony.luck@intel.com, kanaka.d.juvva@intel.com
Subject: [PATCH V4 0/7] x86/intel_rdt: Intel Cache Allocation Technology
Date: Tue, 24 Feb 2015 15:16:37 -0800
Message-Id: <1424819804-4082-1-git-send-email-vikas.shivappa@linux.intel.com>
Sender: linux-kernel-owner@vger.kernel.org
Content-Length: 2634
Lines: 52

This patch adds a new cgroup subsystem to support the new Cache Allocation 
Technology (CAT) feature found in future Intel Xeon Intel processors. CAT is 
part of Resource Director Technology(RDT) or Platform Shared resource control 
which provides support to control Platform shared resources like cache.

Cache Allocation Technology(CAT) provides a way for the Software
(OS/VMM) to restrict cache allocation to a defined 'subset' of cache
which may be overlapping with other 'subsets'. This feature is used
when allocating a line in cache ie when pulling new data into the cache.

This patch series is dependent on the V5 patches for Intel Cache QOS Monitoring 
from Matt since the series also implements a common software cache for the 
IA32_PQR_MSR :
https://lkml.kernel.org/r/1422038748-21397-1-git-send-email-matt@codeblueprint.co.uk
It will apply on the CMT patch series(based on 3.19-rc4) in the link above.

Changes in V4:
- Integrated with the latest V5 CMT patches.
- Changed naming of cgroup to rdt(resource director technology) from cat(cache
  allocation technology). This was done as the RDT is the umbrella term
  for platform shared resources allocation. Hence in future it would be easier 
  to add resource allocation to the same cgroup
- Naming changes also applied to a lot of other data structures/APIs.
- Added documentation on cgroup usage for cache allocation to address a lot of
  questions from various academic and industry regarding cache allocation 
  usage.

Changes in V3:
- Implements a common software cache for IA32_PQR_MSR
- Implements support for hsw CAT enumeration. This does not use the brand
  strings like earlier version but does a probe test. The probe test is done 
  only on hsw family of processors
- Made a few coding convention, name changes
- Check for lock being held when ClosID manipulation happens

Changes in V2:
- Removed HSW specific enumeration changes. Plan to include it later as a
  seperate patch.  
- Fixed the code in prep_arch_switch to be specific for x86 and removed
  x86 defines.
- Fixed cbm_write to not write all 1s when a cgroup is freed.
- Fixed one possible memory leak in init.  
- Changed some of manual bitmap
  manipulation to use the predefined bitmap APIs to make code more readable
- Changed name in sources from cqe to cat
- Global cat enable flag changed to static_key and disabled cgroup early_init
      
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