Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752632AbbBYNKp (ORCPT ); Wed, 25 Feb 2015 08:10:45 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53538 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751590AbbBYNKn (ORCPT ); Wed, 25 Feb 2015 08:10:43 -0500 Message-ID: <54EDC9CD.2000706@codeaurora.org> Date: Wed, 25 Feb 2015 18:40:37 +0530 From: Archit Taneja User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 To: Georgi Djakov , sboyd@codeaurora.org CC: mturquette@linaro.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support References: <1423249118-22132-1-git-send-email-georgi.djakov@linaro.org> <54EC02D3.6060906@codeaurora.org> <54EC9D83.1000900@linaro.org> In-Reply-To: <54EC9D83.1000900@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1923 Lines: 65 Hi Georgi, On 02/24/2015 09:19 PM, Georgi Djakov wrote: > On 02/24/2015 06:49 AM, Archit Taneja wrote: >> Hi, > [..] >>> + >>> +static struct freq_tbl ftbl_gcc_mdss_pclk[] = { >>> + { .src = P_DSI0_PHYPLL_DSI }, >>> + { } >>> +}; >>> + >>> +static struct clk_rcg2 pclk0_clk_src = { >>> + .cmd_rcgr = 0x4d084, >> >> This should be 0x4d000. Same reason as above. >> >>> + .mnd_width = 8, >>> + .hid_width = 5, >>> + .parent_map = gcc_xo_gpll0_dsiphy_map, >>> + .freq_tbl = ftbl_gcc_mdss_pclk, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "pclk0_clk_src", >>> + .parent_names = gcc_xo_gpll0_dsiphy, >>> + .num_parents = 1, >>> + .ops = &clk_rcg2_ops, >>> + }, >>> +}; >>> + >>> +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { >>> + F(19200000, P_XO, 1, 0, 0), >>> + { } >>> +}; >>> + >>> +static struct clk_rcg2 vsync_clk_src = { >>> + .cmd_rcgr = 0x4d02c, >>> + .hid_width = 5, >>> + .parent_map = gcc_xo_gpll0a_map, >>> + .freq_tbl = ftbl_gcc_mdss_vsync_clk, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "vsync_clk_src", >>> + .parent_names = gcc_xo_gpll0a, >>> + .num_parents = 2, >>> + .ops = &clk_rcg2_ops, >>> + }, >>> +}; >>> + >> I think we can update the clk ops for pclk0_clk_src and byte0_clk_src to clk_pixel_ops and clk_byte_ops respectively too. The set_rate functions in these ops have been modified to make it run with DSI PLL. An Ack by Stephen for this change would be nice, though. Archit -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/