Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752969AbbBYQ6P (ORCPT ); Wed, 25 Feb 2015 11:58:15 -0500 Received: from mail-lb0-f170.google.com ([209.85.217.170]:42272 "EHLO mail-lb0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752646AbbBYQ6M (ORCPT ); Wed, 25 Feb 2015 11:58:12 -0500 MIME-Version: 1.0 In-Reply-To: References: <1423851849-6069-1-git-send-email-sboyd@codeaurora.org> <1423851849-6069-3-git-send-email-sboyd@codeaurora.org> <20150220193552.GE1767@arm.com> <20150220201627.GD24928@codeaurora.org> Date: Wed, 25 Feb 2015 11:58:11 -0500 Message-ID: Subject: Re: [PATCH v2 2/2] ARM: perf: Add support for Scorpion PMUs From: Ashwin Chaugule To: Stephen Boyd Cc: Will Deacon , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Mark Rutland , Neil Leeder , Ashwin Chaugule , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2480 Lines: 61 On 24 February 2015 at 12:23, Ashwin Chaugule wrote: > On 20 February 2015 at 15:16, Stephen Boyd wrote: >> On 02/20, Will Deacon wrote: >>> On Fri, Feb 13, 2015 at 06:24:09PM +0000, Stephen Boyd wrote: >>> >>> > +static void scorpion_evt_setup(int idx, u32 config_base) >>> > +{ >>> > + u32 val; >>> > + u32 mask; >>> > + u32 vval, fval; >>> > + unsigned int region; >>> > + unsigned int group; >>> > + unsigned int code; >>> > + unsigned int group_shift; >>> > + bool venum_event; >>> > + >>> > + krait_decode_event(config_base, ®ion, &group, &code, &venum_event, >>> > + NULL); >>> > + >>> > + group_shift = group * 8; >>> > + mask = 0xff << group_shift; >>> > + >>> > + /* Configure evtsel for the region and group */ >>> > + if (venum_event) >>> > + val = SCORPION_VLPM_GROUP0; >>> > + else >>> > + val = scorpion_get_pmresrn_event(region); >>> > + val += group; >>> > + /* Mix in mode-exclusion bits */ >>> > + val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); >>> > + armv7_pmnc_write_evtsel(idx, val); >>> > + >>> > + asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); >>> >>> What's this guy doing? >> >> This is the same as Krait. It's clearing some implementation >> defined register. From what I can tell it's a per-event register >> (i.e. PMSELR decides which event this register write actually >> affects) and we do this here to reset this register to some >> defined value, zero. Otherwise the reset value of this register >> is UNPREDICTABLE and that would be bad. I think we might be able >> to move it to the pmu reset path, but I don't know. Ashwin? > Its a count control register (PMxEVCNTCR). Theres various conditions on which you can select when to start/stop counting. e.g. start when another counter register overflows. Setting it to 0 was the recommended default value on Scorpions and Kraits. Reset value is unpredictable. So, just need to make sure this is set every time a counter is setup. Will that still work if this is moved to the reset path? Cheers, Ashwin. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/