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From: Pranith Kumar <bobby.prani@gmail.com>
Date: Fri, 27 Feb 2015 14:15:57 -0500
Message-ID: <CAJhHMCBJB8Ca1bdapoOx9ecxAwxEPy+X5jv1VCnkCu_GRpyF8Q@mail.gmail.com>
Subject: Re: [RFC PATCH] ARM64: cmpxchg.h: Clear the exclusive access bit on fail
To: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <Catalin.Marinas@arm.com>,
        Steve Capper <steve.capper@linaro.org>,
        Will Deacon <Will.Deacon@arm.com>,
        open list <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
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On Fri, Feb 27, 2015 at 2:08 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Feb 27, 2015 at 06:44:19PM +0000, Pranith Kumar wrote:
>> On Fri, Feb 27, 2015 at 1:33 PM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > It's either badly formatted or I don't get it. Are the "stxr x1" and
>> > "stxr x7" happening on the same CPU (P0)? If yes, that's badly written
>> > code, not even architecturally compliant (you are not allowed other
>> > memory accesses between ldxr and stxr).
>>
>> OK. Is that the same case with ldaxr (acquire) and stlxr (release)?
>> AFAIK, memory accesses between acquire and release exclusive
>> operations are allowed.
>
> The restriction on memory accesses in the middle of a load-exclusive
> store-exclusive sequence applies to all the load/store-exclusive
> variants, including ldaxr and stlxr.
>

Thanks Mark. I am trying to see where this restriction is documented.
Looking at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/a64_data_transfer_alpha.html
I do not see that mentioned. The only restriction relevant is that a
stxr should use the same address as the most recent ldxr.

Could you please point me to the relevant documentation?

Thanks!
-- 
Pranith
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