Message-ID: <551BD241.4060207@redhat.com>
Date: Wed, 01 Apr 2015 13:10:57 +0200
From: Denys Vlasenko <dvlasenk@redhat.com>
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To: Brian Gerst <brgerst@gmail.com>
CC: Ingo Molnar <mingo@kernel.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Steven Rostedt <rostedt@goodmis.org>, Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Andy Lutomirski <luto@amacapital.net>, Oleg Nesterov <oleg@redhat.com>,
        Frederic Weisbecker <fweisbec@gmail.com>,
        Alexei Starovoitov <ast@plumgrid.com>, Will Drewry <wad@chromium.org>,
        Kees Cook <keescook@chromium.org>,
        the arch/x86 maintainers <x86@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions
References: <1427821211-25099-1-git-send-email-dvlasenk@redhat.com>	<1427821211-25099-7-git-send-email-dvlasenk@redhat.com> <CAMzpN2iWm5r-n21yEJo11eNPhkFqcLo7OnPqGunJoRfKEkEhtg@mail.gmail.com>
In-Reply-To: <CAMzpN2iWm5r-n21yEJo11eNPhkFqcLo7OnPqGunJoRfKEkEhtg@mail.gmail.com>
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On 04/01/2015 12:21 AM, Brian Gerst wrote:
> On Tue, Mar 31, 2015 at 1:00 PM, Denys Vlasenko <dvlasenk@redhat.com> wrote:
>> After TESTs, use logically correct JZ mnemonic instead of JE
>> (this doesn't change code).
>>
>> Tidy up CMPW insns:
>>
>> Modern CPUs are not good with 16-bit operations.
>> The instructions with 16-bit immediates are especially bad,
>> on many CPUs they cause length changing prefix stall
>> in the decoders, costing ~6 cycles to recover.
>>
>> Replace CMPWs with CMPLs.
>> Of these, for form with 8-bit sign-extended immediates
>> it is a win because they are smaller now
>> (no 0x66 prefix anymore);
>> ones with 16-bit immediates are faster.
>>
>> @@ -708,7 +708,7 @@ END(sysenter_badsys)
>>  #ifdef CONFIG_X86_ESPFIX32
>>         movl %ss, %eax
>>         /* see if on espfix stack */
>> -       cmpw $__ESPFIX_SS, %ax
>> +       cmpl $__ESPFIX_SS, %eax
>>         jne 27f
>>         movl $__KERNEL_DS, %eax
>>         movl %eax, %ds
> 
> This is incorrect.  32-bit reads from a segment register are not
> zero-extended.  The upper 16 bits are implementation-defined.  Most
> processors will clear them but it's not guaranteed.

I did not know that. I was sure they are always zero extended.


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