Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752748AbbDBAcI (ORCPT ); Wed, 1 Apr 2015 20:32:08 -0400 Received: from mail-wg0-f53.google.com ([74.125.82.53]:35136 "EHLO mail-wg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751541AbbDBAcF (ORCPT ); Wed, 1 Apr 2015 20:32:05 -0400 MIME-Version: 1.0 In-Reply-To: References: <1427821211-25099-1-git-send-email-dvlasenk@redhat.com> <1427821211-25099-7-git-send-email-dvlasenk@redhat.com> <551BD241.4060207@redhat.com> <551C5A73.3050109@redhat.com> Date: Wed, 1 Apr 2015 20:32:03 -0400 Message-ID: Subject: Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions From: Brian Gerst To: Linus Torvalds Cc: Denys Vlasenko , Ingo Molnar , Steven Rostedt , Borislav Petkov , "H. Peter Anvin" , Andy Lutomirski , Oleg Nesterov , Frederic Weisbecker , Alexei Starovoitov , Will Drewry , Kees Cook , "the arch/x86 maintainers" , Linux Kernel Mailing List Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2233 Lines: 54 On Wed, Apr 1, 2015 at 6:14 PM, Linus Torvalds wrote: > On Wed, Apr 1, 2015 at 1:52 PM, Denys Vlasenko wrote: >> >> BTW, AMD64 docs do explicitly say that MOVs from segment registers >> to gpregs are zero-extending. > > Yeah, I think anything even *remotely* recent enough to do 64-bit does > zero-extending. > > Even on the 32-bit side, anything that does register renaming is much > better off with zero-extension than with partial register writes. > > And I found the "push" thing. It's actually documented: > > "When pushing a segment selector onto the stack, the Pentium 4, > Intel Xeon, P6 family, and Intel486 processors > decrement the ESP register by the operand size and then write 2 bytes. > If the operand size is 32-bits, the upper > two bytes of the write are not modified" > > but I can't find any similar documentation for the "mov > Sreg->register" thing. So now I'm starting to doubt my own memory. > > Linus It's in the description of MOV: "When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand. If the register is a destination operand, the resulting value in the two high-order bytes of the register is implementation dependent. For the Pentium 4, Intel Xeon, and P6 family processors, the two high-order bytes are filled with zeros; for earlier 32-bit IA-32 processors, the two high order bytes are undefined." AMD will always zero-extend, although this applies specifically to 64-bit processors: "When reading segment-registers with a 32-bit operand size, the processor zero-extends the 16-bit selector results to 32 bits. When reading segment-registers with a 64-bit operand size, the processor zero-extends the 16-bit selector to 64 bits." So I think it's safe to assume zero-extension on 64-bit, but not 32-bit. -- Brian Gerst -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/