Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752350AbbDBFuv (ORCPT ); Thu, 2 Apr 2015 01:50:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:33242 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751255AbbDBFut (ORCPT ); Thu, 2 Apr 2015 01:50:49 -0400 From: Archit Taneja To: sboyd@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja Subject: [PATCH v2] clk: qcom: Add EBI2 clocks for IPQ806x Date: Thu, 2 Apr 2015 11:20:41 +0530 Message-Id: <1427953841-4147-1-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2758 Lines: 85 The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja --- v2: - removed hwcg_reg/bit entires in ebi2_aon_clk as they only apply to ebi2_clk. - This was originally a part of the qcom nand controller series. Separating it out so that it's already there before qcom nand is merged. drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index cbdc31d..f7e2d07 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -2170,6 +2170,36 @@ static struct clk_branch usb_fs1_h_clk = { }, }; +static struct clk_branch ebi2_clk = { + .hwcg_reg = 0x3b00, + .hwcg_bit = 6, + .halt_reg = 0x2fcc, + .halt_bit = 1, + .clkr = { + .enable_reg = 0x3b00, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ebi2_clk", + .ops = &clk_branch_ops, + .flags = CLK_IS_ROOT, + }, + }, +}; + +static struct clk_branch ebi2_aon_clk = { + .halt_reg = 0x2fcc, + .halt_bit = 0, + .clkr = { + .enable_reg = 0x3b00, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "ebi2_always_on_clk", + .ops = &clk_branch_ops, + .flags = CLK_IS_ROOT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2273,6 +2303,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, + [EBI2_CLK] = &ebi2_clk.clkr, + [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 04fb29a..ebd63fd 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -288,5 +288,6 @@ #define UBI32_CORE2_CLK_SRC 278 #define UBI32_CORE1_CLK 279 #define UBI32_CORE2_CLK 280 +#define EBI2_AON_CLK 281 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/