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Date: Tue, 13 Feb 2001 07:06:44 -0600 (CST)
From: Jeff Garzik <jgarzik@mandrakesoft.mandrakesoft.com>
To: Jes Sorensen <jes@linuxcare.com>
cc: G?rard Roudier <groudier@club-internet.fr>,
        Alan Cox <alan@lxorguk.ukuu.org.uk>, Donald Becker <becker@scyld.com>,
        Linux-Kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] starfire reads irq before pci_enable_device.
In-Reply-To: <d3n1brafoj.fsf@lxplus015.cern.ch>
Message-ID: <Pine.LNX.3.96.1010213070337.31857F-100000@mandrakesoft.mandrakesoft.com>
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On 12 Feb 2001, Jes Sorensen wrote:
> >>>>> "G?rard" == G?rard Roudier <groudier@club-internet.fr> writes:
> G?rard> In PCI, it is the Memory Write and Invalidate PCI transaction
> G?rard> that is intended to allow core-logics to optimize DMA this
> G?rard> way. For normal Memory Write PCI transactions or when the
> G?rard> core-logic is aliasing MWI to MW, the snooping may well
> G?rard> happen. All that stuff, very probably, varies a lot depending
> G?rard> on the core-logic.
> 
> In fact one has to look out for this and disable the feature in some
> cases. On the acenic not disabling Memory Write and Invalidate costs
> ~20% on performance on some systems.

And in another message, On Mon, 12 Feb 2001, David S. Miller wrote:
> 3) The acenic/gbit performance anomalies have been cured
>    by reverting the PCI mem_inval tweaks.


Just to be clear, acenic should or should not use MWI?

And can a general rule be applied here?  Newer Tulip hardware also
has the ability to enable/disable MWI usage, IIRC.

	Jeff




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