Message-ID: <5527D631.4090905@redhat.com>
Date: Fri, 10 Apr 2015 15:54:57 +0200
From: Denys Vlasenko <dvlasenk@redhat.com>
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To: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@kernel.org>
CC: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Jason Low <jason.low2@hp.com>, Peter Zijlstra <peterz@infradead.org>,
        Davidlohr Bueso <dave@stgolabs.net>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Aswin Chandramouleeswaran <aswin@hp.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Andy Lutomirski <luto@amacapital.net>, Brian Gerst <brgerst@gmail.com>,
        "H. Peter Anvin" <hpa@zytor.com>, Thomas Gleixner <tglx@linutronix.de>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCH] x86: Align jump targets to 1 byte boundaries
References: <20150409175652.GI6464@linux.vnet.ibm.com> <CA+55aFzXMDjQQ7jTjsPdh1RikXfgV7OCd-+13cz06MOmDBA33w@mail.gmail.com> <CA+55aFwZWi6ecDmVsMBQJTrgrW3GD2DaRtpiOspe=5amR1=dNg@mail.gmail.com> <20150409183926.GM6464@linux.vnet.ibm.com> <20150410090051.GA28549@gmail.com> <20150410091252.GA27630@gmail.com> <20150410092152.GA21332@gmail.com> <20150410111427.GA30477@gmail.com> <20150410112748.GB30477@gmail.com> <20150410120846.GA17101@gmail.com> <20150410131929.GE28074@pd.tnic>
In-Reply-To: <20150410131929.GE28074@pd.tnic>
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On 04/10/2015 03:19 PM, Borislav Petkov wrote:
> On Fri, Apr 10, 2015 at 02:08:46PM +0200, Ingo Molnar wrote:
>> Now, the usual justification for jump target alignment is the 
>> following: with 16 byte instruction-cache cacheline sizes, if a 
> 
> You mean 64 bytes?
> 
> Cacheline size on modern x86 is 64 bytes. The 16 alignment is probably
> some branch predictor stride thing.

IIRC it's a maximum decode bandwidth. Decoders on the most powerful
x86 CPUs, both Intel and AMD, attempt to decode in one cycle
up to four instructions. For this they fetch up to 16 bytes.
If cacheline ends before 16 bytes are available, then decode
will operate on fewer bytes, or it will wait for next cacheline
to be fetched.


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