Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755509AbbDJSIs (ORCPT ); Fri, 10 Apr 2015 14:08:48 -0400 Received: from mail-ob0-f176.google.com ([209.85.214.176]:35553 "EHLO mail-ob0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751687AbbDJSIp (ORCPT ); Fri, 10 Apr 2015 14:08:45 -0400 Message-ID: <552811A9.1090009@gmail.com> Date: Fri, 10 Apr 2015 13:08:41 -0500 From: Dinh Nguyen User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Doug Anderson , Dinh Nguyen CC: "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , setka@vsis.cz, Seungwon Jeon , Jaehoon Chung , Chris Ball , Ulf Hansson , Alexandru Stan , =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= Subject: Re: [PATCH] mmc: dw_mmc: add fixed divider for ciu_clk on SoCFPGA References: <1428674162-11200-1-git-send-email-dinguyen@opensource.altera.com> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2001 Lines: 53 On 4/10/15 10:15 AM, Doug Anderson wrote: > Dinh, > > On Fri, Apr 10, 2015 at 6:56 AM, wrote: >> From: Dinh Nguyen >> >> The ciu_clk(Card Interface Unit Clock) on the SoCFPGA platform has a fixed >> divider of 4. Add the fixed clock divide code in the platform's clock >> setup code. > > It might actually be better to do this a different way for SoCFPGA. I > sorta wish we had done it differently for Rockchip as well, but at > this point you end up with the complexity of changing device tree > bindings in conjunction with code and it gets ugly. Yes, I started going down this path and realized that. > > Specifically, you've probably got the following clocks: > > SD_prediv = 400MHz > -> SD postdiv = 100MHz > -> SD sample = 100MHz, shifted > -> SD drive = 100MHz, shifted > > Right now you're specifying "SD_prediv" as the SD card clock. If you > instead expose "SD postdiv" as a new clock (from your clock driver) > that is "SD prediv" divided by 4 then you'll magically get all the > behavior that you want with no modifications to dw_mmc. Just make > sure that "SD postdiv" passes on rate changes to its parent (that's > just a flag in the common clock framework). > That's a great idea, thanks for pointing that out. > > At some point in time you'll also want to expose the sample and drive > clocks once you get UHS modes working. Alexandru posted some patches > for this a while ago to support tuning in dw_mmc using just drive and > sample clocks, but the patch still needed some more work. Either he > or I will probably pick it up again soon. I think I have already done this by representing the sdmmc_clk with a "clk-phase" property for this clock. Dinh -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/