Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753728AbbDMRrd (ORCPT ); Mon, 13 Apr 2015 13:47:33 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:63620 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750833AbbDMRr1 (ORCPT ); Mon, 13 Apr 2015 13:47:27 -0400 X-AuditID: cbfee61a-f79516d000006302-64-552c012abaa6 From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH 1/4] clk: samsung: exynos5250: add cpu clock configuration data and instantiate cpu clock Date: Mon, 13 Apr 2015 19:46:59 +0200 Message-id: <1428947223-17268-2-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1428947223-17268-1-git-send-email-b.zolnierkie@samsung.com> References: <1428947223-17268-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsVy+t9jQV0tRp1QgzNz5S02zljPanH9y3NW i/+PXrNaHP1dYNG74CqbRf/j18wWXw+vYLR483Azo8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCye TrjIZnH4TTurRccyRotVu/4wWmz86uEg6PH3+XUWj52z7rJ7bFrVyeZx59oeNo/NS+o9+ras YvTYfm0es8fnTXIBHFFcNimpOZllqUX6dglcGT27L7AV7Jer+NV/kqWBcbVkFyMnh4SAicSK i9vYIWwxiQv31rN1MXJxCAlMZ5TYcq2LHcL5zSjx9Mc2JpAqNgEriYntqxhBEiICHxglXr/7 BtbCLDCfWWLC01MsXYwcHMIC2RLdDYUgJouAqsT+/3wgvbwCHhJHFjWBVUgIKEjMmWQDEuYU 8JT4MfM4G4gtBFTyrekA0wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcxgsP5mdQO xpUNFocYBTgYlXh4L9zRChViTSwrrsw9xCjBwawkwqvySTtUiDclsbIqtSg/vqg0J7X4EKM0 B4uSOO8cXblQIYH0xJLU7NTUgtQimCwTB6dUA2N6efG1ycpemycsnZnMkznpJ5PHrOTsJbOn Me0orF3Gtqzg8fUoppa658Kr/b6eyg5dnuns+HinVUjH1bo775b1Gc7mTP4efvjEppnifsrT uUX3uBrOZ3Hs1E92Ovbtyczjv5X1lf5l/rZ4pWbcmsbqZ2XOXcx1rHue4OnKqVb120sqvGbO OaHEUpyRaKjFXFScCAAOhFN8YwIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4057 Lines: 96 From: Thomas Abraham With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Changes by Bartlomiej: - split Exynos5250 support from the original patch - moved E5250_CPU_DIV[0,1]() macros to clk-exynos5250.c Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Signed-off-by: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos5250.c | 31 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5250.h | 1 + 2 files changed, 32 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 70ec3d2..d87f34d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -748,6 +749,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { VPLL_LOCK, VPLL_CON0, NULL), }; +#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \ + ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((periph) << 12) | ((acp) << 8) | ((cpud) << 4))) +#define E5250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | (copy)) + +static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { + { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 0 }, +}; + static const struct of_device_id ext_clk_match[] __initconst = { { .compatible = "samsung,clock-xxti", .data = (void *)0, }, { }, @@ -797,6 +824,10 @@ static void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks)); samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d), + CLK_CPU_HAS_DIV1); /* * Enable arm clock down (in idle) and set arm divider diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 4273891d..8183d1c 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -21,6 +21,7 @@ #define CLK_FOUT_CPLL 6 #define CLK_FOUT_EPLL 7 #define CLK_FOUT_VPLL 8 +#define CLK_ARM_CLK 9 /* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128 -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/