Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753623AbbDNRsl (ORCPT ); Tue, 14 Apr 2015 13:48:41 -0400 Received: from down.free-electrons.com ([37.187.137.238]:49244 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751046AbbDNRsc (ORCPT ); Tue, 14 Apr 2015 13:48:32 -0400 Date: Tue, 14 Apr 2015 19:48:26 +0200 From: Boris Brezillon To: Michael Turquette Cc: "Nicolas Ferre" , "Jean-Christophe Plagniol-Villard" , "Alexandre Belloni" , "Jonas Andersson" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH] clk: at91: pll: fix input range validity check Message-ID: <20150414194826.1c43aff1@bbrezillon> In-Reply-To: <20150413043725.19585.5717@quantum> References: <1427594023-9697-1-git-send-email-boris.brezillon@free-electrons.com> <20150413043725.19585.5717@quantum> X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2028 Lines: 57 Hi Mike, On Sun, 12 Apr 2015 21:37:25 -0700 Michael Turquette wrote: > Quoting Boris Brezillon (2015-03-28 18:53:43) > > The PLL impose a certain input range to work correctly, but it appears that > > this input range does not apply on the input clock (or parent clock) but > > on the input clock after it has passed the PLL divisor. > > Fix the implementation accordingly. > > > > Cc: # v3.14+ > > Signed-off-by: Boris Brezillon > > Reported-by: Jonas Andersson > > Hi Boris, > > OK, so this patch along with your two previous submissions kind of > tackle some of items I mentioned earlier today[0]. > > Does this patch, combined with your two prior patches[1][2] resolve the > issue you brought up in your "Propagating clock rate constraints" > thread[3]? Unfortunately it doesn't (though it does resolve one of my issues, so I definitely need that patch :-)). Take the following case: 1/ clock X takes clock Y as its parent (let's say clock X is a clock divider) 2/ user U claims clock X and configure X's rate (X then propagates rate change to Y) and assign a specific supported rate range to X 2/ user V claims clock Y and sets a specific rate As of today, the constraint U has set on clock X is not propagated to clock Y, which means user V might configure a rate that is not fulfilling users V constraint, and the clk infrastructure won't complain (actually it won't detect it). Here's what I would expect: if a (MIN -> MAX) constraint is set on clock X the (MIN * XDIV -> MAX * XDIV) constraint should be propagated to clock Y. Am I wrong ? Best Regards, -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/