Date: Wed, 15 Apr 2015 20:36:25 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Kan Liang <kan.liang@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@kernel.org, acme@infradead.org,
        eranian@google.com, andi@firstfloor.org
Subject: Re: [PATCH V6 4/6] perf, x86: handle multiple records in PEBS buffer
Message-ID: <20150415183625.GY23123@twins.programming.kicks-ass.net>
References: <1428597466-8154-1-git-send-email-kan.liang@intel.com>
 <1428597466-8154-5-git-send-email-kan.liang@intel.com>
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On Thu, Apr 09, 2015 at 12:37:44PM -0400, Kan Liang wrote:
> +/* Clear all non-PEBS bits */
> +static u64
> +nonpebs_bit_clear(u64 pebs_status)
> +{
> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +	struct perf_event *event;
> +	int bit;
> +
> +	for_each_set_bit(bit, (unsigned long *)&pebs_status, 64) {
> +
> +		if (bit >= x86_pmu.max_pebs_events)
> +			clear_bit(bit, (unsigned long *)&pebs_status);
> +		else {
> +			event = cpuc->events[bit];
> +			WARN_ON_ONCE(!event);
> +
> +			if (!event->attr.precise_ip)
> +				clear_bit(bit, (unsigned long *)&pebs_status);
> +		}
> +	}
> +
> +	return pebs_status;
> +}

What was wrong with:

	status = p->status & cpuc->pebs_enabled;

?

We use the same index bits in the PEBS_ENABLE MSR as in the status reg,
right? If you're really paranoid you can mask out the high (>31) bits
too I suppose.
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