Date: Thu, 16 Apr 2015 08:30:56 +0200
From: Rogier Wolff <R.E.Wolff@bitwizard.nl>
To: Noralf =?iso-8859-1?Q?Tr=F8nnes?= <noralf@tronnes.org>
Cc: Martin Sperl <martin@sperl.org>, dmaengine@vger.kernel.org,
        vinod.koul@intel.com, linux-kernel@vger.kernel.org,
        jonathan@raspberrypi.org, linux-rpi-kernel@lists.infradead.org,
        dan.j.williams@intel.com
Subject: Re: [PATCH] dmaengine: bcm2835: Add slave dma support
Message-ID: <20150416063055.GH23239@bitwizard.nl>
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On Wed, Apr 15, 2015 at 08:53:07PM +0200, Noralf Tr?nnes wrote:

> A 16-bit register can't hold a value of 65536.
> Either the max value is 65535 or the register is 17-bits wide.

It is common for hardware registers to have the value "0" mean 65536
in case of a 16-bit register.

The hardware would then FIRST decrement the register and THEN check
for zero. This results in the behaviour that "1" requires one cycle to
complete, "10" requires ten cycles, and "0" means the same as the
total number of bitpatterns possible in the register. (256 for an
8-bit register, 65536 for a 16-bit register).

Another way to implement such a register in hardware would "check for
zero" first, and not do antyhing if the register equals zero. This
results in differnet behaviour for the "0" value.

That said: IMHO, the overhead of setting up 2 transfers for each 64k
block as opposed to only one results in such a small performance
penalty that I'd prefer to play it safe unless you're very sure you
can adequately test it. (Another option would be to set the maximum
transfer size to 0xf000: 60kbytes. Less than 10% extra transfers in 
the long run than when aiming for the edge...)

	Roger. 

-- 
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