Date: Fri, 17 Apr 2015 10:11:00 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Kan Liang <kan.liang@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@kernel.org, acme@infradead.org,
        eranian@google.com, andi@firstfloor.org
Subject: Re: [PATCH V6 4/6] perf, x86: handle multiple records in PEBS buffer
Message-ID: <20150417081100.GZ24151@twins.programming.kicks-ass.net>
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On Thu, Apr 16, 2015 at 02:53:42PM +0200, Peter Zijlstra wrote:
> When the PEBS interrupt threshold is larger than one record and the
> machine supports multiple PEBS events, the records of these events are
> mixed up and we need to demultiplex them.
> 
> Demuxing the records is hard because the hardware is deficient. The
> hardware has two issues that, when combined, create impossible scenarios
> to demux.
> 
> The first issue is that the 'status' field of the PEBS record is a copy
> of the GLOBAL_STATUS MSR at PEBS assist time. To see why this is a
> problem let us first describe the regular PEBS cycle:
> 
>  A) the CTRn value reaches 0:
>     - the corresponding bit in GLOBAL_STATUS gets set
>     - we start arming the hardware assist
> 
>     < some unspecified amount of time later --
>         this could cover multiple events of interest >
> 
>  B) the hardware assist is armed, any next event will trigger it
> 
>  C) a matching event happens:
>     - the hardware assist triggers and generates a PEBS record
>       this includes a copy of GLOBAL_STATUS at this moment
>     - if we auto-reload we (re)set CTRn

Is this actually true? Do we reload here or on A ?

>     - we clear the relevant bit in GLOBAL_STATUS
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