Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966275AbbDQOZo (ORCPT ); Fri, 17 Apr 2015 10:25:44 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:24353 "EHLO smtp2-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965232AbbDQOZj (ORCPT ); Fri, 17 Apr 2015 10:25:39 -0400 From: Alban Bedel To: linux-mips@linux-mips.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper , Ralf Baechle , Alban Bedel , Andrew Bresticker , Qais Yousef , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] devicetree: Add bindings for the ATH79 DDR controllers Date: Fri, 17 Apr 2015 16:24:18 +0200 Message-Id: <1429280669-2986-4-git-send-email-albeu@free.fr> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1429280669-2986-1-git-send-email-albeu@free.fr> References: <1429280669-2986-1-git-send-email-albeu@free.fr> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2208 Lines: 60 The DDR controller of the ARxxx and AR9xxx famillies provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel --- .../memory-controllers/ath79-ddr-controller.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt new file mode 100644 index 0000000..5541eed --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt @@ -0,0 +1,35 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller + +The DDR controller of the ARxxx and AR9xxx famillies provides an interface +to flush the FIFO between various devices and the DDR. This is mainly used +by the IRQ controller to flush the FIFO before running the interrupt handler +of such devices. + +Required properties: + +- compatible: has to be "qca,-ddr-controller", + "qca,[ar7100|ar7240]-ddr-controller" as fallback. + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as + fallback, otherwise "qca,ar7240-ddr-controller" should be used. +- reg: Base address and size of the controllers memory area +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer + channel + +Example: + + ddr_ctrl: ddr-controller@18000000 { + compatible = "qca,ar9132-ddr-controller", + "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + ... + + cpuintc@0 { + ... + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/