Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752720AbbDSNwI (ORCPT ); Sun, 19 Apr 2015 09:52:08 -0400 Received: from mail-lb0-f177.google.com ([209.85.217.177]:32832 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751979AbbDSNwC (ORCPT ); Sun, 19 Apr 2015 09:52:02 -0400 Message-ID: <5533B300.2050805@cogentembedded.com> Date: Sun, 19 Apr 2015 16:52:00 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Alban Bedel , linux-mips@linux-mips.org CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper , Ralf Baechle , Andrew Bresticker , Qais Yousef , Gabor Juhos , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 03/12] devicetree: Add bindings for the ATH79 DDR controllers References: <1429448288-20742-1-git-send-email-albeu@free.fr> <1429448288-20742-4-git-send-email-albeu@free.fr> In-Reply-To: <1429448288-20742-4-git-send-email-albeu@free.fr> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2556 Lines: 78 Hello. On 4/19/2015 3:57 PM, Alban Bedel wrote: > The DDR controller of the ARxxx and AR9xxx famillies provides an > interface to flush the FIFO between various devices and the DDR. > This is mainly used by the IRQ controller to flush the FIFO before > running the interrupt handler of such devices. > Signed-off-by: Alban Bedel > --- > v2: * Fix the node names to respect ePAPR I don't see where you did this. > --- > .../memory-controllers/ath79-ddr-controller.txt | 35 ++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > new file mode 100644 > index 0000000..5541eed > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > @@ -0,0 +1,35 @@ > +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller > + > +The DDR controller of the ARxxx and AR9xxx famillies provides an interface Families. > +to flush the FIFO between various devices and the DDR. This is mainly used > +by the IRQ controller to flush the FIFO before running the interrupt handler > +of such devices. > + > +Required properties: > + > +- compatible: has to be "qca,-ddr-controller", > + "qca,[ar7100|ar7240]-ddr-controller" as fallback. > + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as > + fallback, otherwise "qca,ar7240-ddr-controller" should be used. > +- reg: Base address and size of the controllers memory area > +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer > + channel > + > +Example: > + > + ddr_ctrl: ddr-controller@18000000 { Should still be "memory-controller@18000000". > + compatible = "qca,ar9132-ddr-controller", > + "qca,ar7240-ddr-controller"; > + reg = <0x18000000 0x100>; > + > + #qca,ddr-wb-channel-cells = <1>; > + }; > + > + ... > + > + cpuintc@0 { "interrupt-controller" here? > + ... > + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; > + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, > + <&ddr_ctrl 0>, <&ddr_ctrl 1>; > + }; WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/