Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755593AbbDUNU5 (ORCPT ); Tue, 21 Apr 2015 09:20:57 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:60614 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752263AbbDUNS7 (ORCPT ); Tue, 21 Apr 2015 09:18:59 -0400 X-AuditID: cbfee61a-f79516d000006302-61-55364e41a442 From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH 3/8] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock Date: Tue, 21 Apr 2015 15:17:53 +0200 Message-id: <1429622278-12216-4-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1429622278-12216-1-git-send-email-b.zolnierkie@samsung.com> References: <1429622278-12216-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsVy+t9jQV1HP7NQg4//JS02zljPanH9y3NW i/+PXrNaHP1dYNG74CqbRf/j18wWXw+vYLR483Azo8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCye TrjIZnH4TTurRccyRotVu/4wWmz86uEg6PH3+XUWj52z7rJ7bFrVyeZx59oeNo/NS+o9+ras YvTYfm0es8fnTXIBHFFcNimpOZllqUX6dglcGT/2djEWfFeteDVhBmsD41L5LkZODgkBE4mp K24zQ9hiEhfurWfrYuTiEBKYzihxbPccZgjnN6PE26bvjCBVbAJWEhPbVzGCJEQEPjBKvH73 DayFWWA+s8SEp6dYQKqEBbIljh+YxdTFyMHBIqAqseJtIUiYV8BDYvuz18wgYQkBBYk5k2xA wpwCnhLnL79kBbGFgEomztrPOIGRdwEjwypG0dSC5ILipPRcQ73ixNzi0rx0veT83E2M4IB+ JrWDcWWDxSFGAQ5GJR7eFRNMQ4VYE8uKK3MPMUpwMCuJ8AoKmYUK8aYkVlalFuXHF5XmpBYf YpTmYFES552jKxcqJJCeWJKanZpakFoEk2Xi4JRqYJyyzyklf9nU60+nCfDxLpVJPNPPJR4W l/q6cl5buLf81GUvLKUrTi8rFWk3UTE9bCO14OG+Fx739Rh4rq810RVcWLmYy9h4hfQ85bW1 j7leiErI5r76t/iRkqW+9LJcDemQN8sZA9+U8Hs8Obf7iPT19HrepxOY9bXP5yX80X1ieVpb b21ZjxJLcUaioRZzUXEiAPOOB5ZkAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4973 Lines: 132 From: Thomas Abraham With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420 support from the original patches - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Signed-off-by: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos5420.c | 58 ++++++++++++++++++++++++++++++-- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 07d666c..9398a2d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), + MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), @@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { KPLL_CON0, NULL), }; +#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ + ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((cpud) << 4))) + +static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 0 }, +}; + +#define E5420_KFC_DIV(kpll, pclk, aclk) \ + ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) + +static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1300000, E5420_KFC_DIV(3, 5, 2), }, + { 1200000, E5420_KFC_DIV(3, 5, 2), }, + { 1100000, E5420_KFC_DIV(3, 5, 2), }, + { 1000000, E5420_KFC_DIV(3, 5, 2), }, + { 900000, E5420_KFC_DIV(3, 5, 2), }, + { 800000, E5420_KFC_DIV(3, 5, 2), }, + { 700000, E5420_KFC_DIV(3, 4, 2), }, + { 600000, E5420_KFC_DIV(3, 4, 2), }, + { 500000, E5420_KFC_DIV(3, 4, 2), }, + { 400000, E5420_KFC_DIV(3, 3, 2), }, + { 300000, E5420_KFC_DIV(3, 3, 2), }, + { 200000, E5420_KFC_DIV(3, 3, 2), }, + { 0 }, +}; + static const struct of_device_id ext_clk_match[] __initconst = { { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, { }, @@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", + mout_kfc_p[0], mout_kfc_p[1], 0x28200, + exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); + exynos5420_clk_sleep_init(); samsung_clk_of_add_provider(np, ctx); diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 99da0d1..dde9664 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -25,6 +25,8 @@ #define CLK_FOUT_MPLL 10 #define CLK_FOUT_BPLL 11 #define CLK_FOUT_KPLL 12 +#define CLK_ARM_CLK 13 +#define CLK_KFC_CLK 14 /* gate for special clocks (sclk) */ #define CLK_SCLK_UART0 128 -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/