Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755770AbbDUSCL (ORCPT ); Tue, 21 Apr 2015 14:02:11 -0400 Received: from exprod5og121.obsmtp.com ([64.18.0.139]:39879 "EHLO mail-ob0-f178.google.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751006AbbDUSCG (ORCPT ); Tue, 21 Apr 2015 14:02:06 -0400 MIME-Version: 1.0 In-Reply-To: <55366A64.6000907@arm.com> References: <55310050.7000003@arm.com> <227f8c75e04110e279b78512924742ba7c7fe5fc.1429586144.git.dhdang@apm.com> <55366A64.6000907@arm.com> From: Duc Dang Date: Tue, 21 Apr 2015 11:01:35 -0700 Message-ID: Subject: Re: [PATCH v5 2/4] arm64: dts: Add the device tree entry for the APM X-Gene PCIe MSI node To: Marc Zyngier Cc: Bjorn Helgaas , Arnd Bergmann , "grant.likely@linaro.org" , Liviu Dudau , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Tanmay Inamdar , Loc Ho , Feng Kan Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2728 Lines: 67 On Tue, Apr 21, 2015 at 8:19 AM, Marc Zyngier wrote: > On 21/04/15 05:04, Duc Dang wrote: >> There is single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. >> >> Signed-off-by: Duc Dang >> Signed-off-by: Tanmay Inamdar >> --- >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 27 +++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi >> index f1ad9c2..4b719c9 100644 >> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi >> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi >> @@ -354,6 +354,28 @@ >> }; >> }; >> >> + msi: msi@79000000 { >> + compatible = "apm,xgene1-msi"; >> + msi-controller; >> + reg = <0x00 0x79000000 0x0 0x900000>; > > I've been repeatedly puzzled by the size of this region. In patch 1, you > say: > > + * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where > + * n is group number (0..F), x is index of registers in each group (0..7) > + * The registers layout is like following: > + * MSI0IR0 base_addr > + * MSI0IR1 base_addr + 0x10000 > + * ... ... > + * MSI0IR6 base_addr + 0x60000 > + * MSI0IR7 base_addr + 0x70000 > + * MSI1IR0 base_addr + 0x80000 > + * MSI1IR1 base_addr + 0x90000 > + * ... ... > + * MSI1IR7 base_addr + 0xF0000 > + * MSI2IR0 base_addr + 0x100000 > + * ... ... > + * MSIFIR0 base_addr + 0x780000 > + * MSIFIR1 base_addr + 0x790000 > + * ... ... > + * MSIFIR7 base_addr + 0x7F0000 > > which implies that the size of the region is 0x800000. Or is there > something hidden in the last 16 64k pages? The registers listed in the first patch are termination registers. >From offset 0x800000 to 0x8f0000, the MSI controller provides status registers for software to check if there is pending MSI interrupt in each MSI group (in the code we read MSI_INTx registers starting from 0x800000 to check if there is an MSI interrupt pending). > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... Regards, Duc Dang. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/