Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934336AbbDVIOp (ORCPT ); Wed, 22 Apr 2015 04:14:45 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:42868 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932962AbbDVIOm (ORCPT ); Wed, 22 Apr 2015 04:14:42 -0400 X-AuditID: cbfee61a-f79516d000006302-23-55375870ce25 Date: Wed, 22 Apr 2015 10:14:31 +0200 From: Lukasz Majewski To: Bartlomiej Zolnierkiewicz Cc: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Kevin Hilman , Heiko Stuebner , linux-pm@vger.kernel.org, Tomasz Figa , linux-kernel@vger.kernel.org, Chanwoo Choi , linux-samsung-soc@vger.kernel.org, Javier Martinez Canillas , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 6/8] clk: samsung: exynos5800: fix cpu clock configuration data Message-id: <20150422101431.43fafb4e@amdc2363> In-reply-to: <1429622278-12216-7-git-send-email-b.zolnierkie@samsung.com> References: <1429622278-12216-1-git-send-email-b.zolnierkie@samsung.com> <1429622278-12216-7-git-send-email-b.zolnierkie@samsung.com> Organization: SPRC Poland X-Mailer: Claws Mail 3.8.1 (GTK+ 2.24.10; x86_64-pc-linux-gnu) MIME-version: 1.0 Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsVy+t9jQd2CCPNQg7WbzS02zljPanH9y3NW i/+PXrNaHP1dYNG74CqbRf/j18wWXw+vYLTY9Pgaq8XlXXPYLD73HmG0mHF+H5PF0wkX2SwO v2lntehYxmixatcfRouNXz0cBDz+Pr/O4rFz1l12j02rOtk87lzbw+axeUm9R9+WVYwe26/N Y/b4vEkugCOKyyYlNSezLLVI3y6BK+Puo9fMBU+lKja9/sLWwPhJtIuRk0NCwERi2awDjBC2 mMSFe+vZQGwhgemMEg3TqroYuYDsN4wS07vugiVYBFQlJvccArPZBPQkPt99ygRiiwhYSKxd 8ZYFxGYWOMkiMe1NMogtLBAq8WT+NHYQmxeo/u23LWD1nAKeEu9fz2eGWNDOKPH3yGuwIn4B SYn2fz+YIS6ykzj3aQNUs6DEj8n3oBZoSWze1sQKYctLbF7zlnkCo+AsJGWzkJTNQlK2gJF5 FaNoakFyQXFSeq6hXnFibnFpXrpecn7uJkZwvD2T2sG4ssHiEKMAB6MSDy8Dl3moEGtiWXFl 7iFGCQ5mJRHeZFugEG9KYmVValF+fFFpTmrxIUZpDhYlcd45unKhQgLpiSWp2ampBalFMFkm Dk6pBsYihsNME97U8h9kXGfdzJcjU75ugfGNKHu7vAeLMnKzdTbs1t149jfTFov1fLvN+5li 0r63zDEVV+j8acE4s5eFv71vkV0hx/FZB/+9FfVq+5DZ/zKAX+Nlhba5p43FgSPzO0Nf8h1V tHI4rvri8exLvk7PAxJY2g8f+uTH8OVpR8DGvfrZy5RYijMSDbWYi4oTARRVpLKzAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3583 Lines: 96 Hi Bartlomiej, > Fix cpu clock configuration data for Exynos5800 (it uses > higher PCLK_DBG divider values than Exynos5420 and supports > additional frequencies). > > Based on Hardkernel's kernel for ODROID-XU3 board. > > Cc: Tomasz Figa > Cc: Mike Turquette > Cc: Javier Martinez Canillas > Cc: Thomas Abraham > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > drivers/clk/samsung/clk-exynos5420.c | 36 > +++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), > 3 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c > b/drivers/clk/samsung/clk-exynos5420.c index 9398a2d..462aaee 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data > exynos5420_eglclk_d[] __initconst = { { 0 }, > }; > > +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] > __initconst = { > + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, > + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, > + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, > + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, > + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, > + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, > + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, > + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, > + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, > + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, > + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, > + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, > + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, > + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, > + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, > + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, > + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, > + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, > + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, > + { 0 }, > +}; > + > #define E5420_KFC_DIV(kpll, pclk, > aclk) \ ((((kpll) << 24) | > ((pclk) << 20) | ((aclk) << 4))) > static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] > __initconst = { > + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ > { 1300000, E5420_KFC_DIV(3, 5, 2), }, > { 1200000, E5420_KFC_DIV(3, 5, 2), }, > { 1100000, E5420_KFC_DIV(3, 5, 2), }, > @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct > device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); > } > > - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", > - mout_cpu_p[0], mout_cpu_p[1], 0x200, > - exynos5420_eglclk_d, > ARRAY_SIZE(exynos5420_eglclk_d), 0); > + if (soc == EXYNOS5420) { > + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", > + mout_cpu_p[0], mout_cpu_p[1], 0x200, > + exynos5420_eglclk_d, > ARRAY_SIZE(exynos5420_eglclk_d), 0); > + } else { > + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", > + mout_cpu_p[0], mout_cpu_p[1], 0x200, > + exynos5800_eglclk_d, > ARRAY_SIZE(exynos5800_eglclk_d), 0); > + } > exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", > mout_kfc_p[0], mout_kfc_p[1], 0x28200, > exynos5420_kfcclk_d, > ARRAY_SIZE(exynos5420_kfcclk_d), 0); Reviewed-by: Lukasz Majewski -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/