Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758448AbbDXQss (ORCPT ); Fri, 24 Apr 2015 12:48:48 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14488 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758302AbbDXQsl (ORCPT ); Fri, 24 Apr 2015 12:48:41 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 24 Apr 2015 09:47:40 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Rhyland Klein Subject: [PATCH 04/19] clk: tegra: pll: simplify clk_enable_path Date: Fri, 24 Apr 2015 12:47:44 -0400 Message-ID: <1429894079-25052-5-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1429894079-25052-1-git-send-email-rklein@nvidia.com> References: <1429894079-25052-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4749 Lines: 160 Instead of having multiple similar wrapper functions for _clk_pll_[enable|disable], we can simplify it to single wrappers and use checks to avoid the logic we don't want to use. Signed-off-by: Rhyland Klein --- drivers/clk/tegra/clk-pll.c | 79 ++++++++++++++----------------------------- 1 file changed, 25 insertions(+), 54 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index b9a739ce4b98..d287df90cfc0 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -332,11 +332,20 @@ static int clk_pll_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); unsigned long flags = 0; + + u32 val; int ret; if (pll->lock) spin_lock_irqsave(pll->lock, flags); + if (pll->params->iddq_reg) { + val = pll_readl(pll->params->iddq_reg, pll); + val &= ~BIT(pll->params->iddq_bit_idx); + pll_writel(val, pll->params->iddq_reg, pll); + udelay(2); + } + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); @@ -351,12 +360,20 @@ static void clk_pll_disable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); unsigned long flags = 0; + u32 val; if (pll->lock) spin_lock_irqsave(pll->lock, flags); _clk_pll_disable(hw); + if (pll->params->iddq_reg) { + val = pll_readl(pll->params->iddq_reg, pll); + val |= BIT(pll->params->iddq_bit_idx); + pll_writel(val, pll->params->iddq_reg, pll); + udelay(2); + } + if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); } @@ -876,52 +893,6 @@ static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, return 0; } -static int clk_pll_iddq_enable(struct clk_hw *hw) -{ - struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long flags = 0; - - u32 val; - int ret; - - if (pll->lock) - spin_lock_irqsave(pll->lock, flags); - - val = pll_readl(pll->params->iddq_reg, pll); - val &= ~BIT(pll->params->iddq_bit_idx); - pll_writel(val, pll->params->iddq_reg, pll); - udelay(2); - - _clk_pll_enable(hw); - - ret = clk_pll_wait_for_lock(pll); - - if (pll->lock) - spin_unlock_irqrestore(pll->lock, flags); - - return 0; -} - -static void clk_pll_iddq_disable(struct clk_hw *hw) -{ - struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long flags = 0; - u32 val; - - if (pll->lock) - spin_lock_irqsave(pll->lock, flags); - - _clk_pll_disable(hw); - - val = pll_readl(pll->params->iddq_reg, pll); - val |= BIT(pll->params->iddq_bit_idx); - pll_writel(val, pll->params->iddq_reg, pll); - udelay(2); - - if (pll->lock) - spin_unlock_irqrestore(pll->lock, flags); -} - static int _calc_dynamic_ramp_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) @@ -1518,8 +1489,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, defined(CONFIG_ARCH_TEGRA_132_SOC) static const struct clk_ops tegra_clk_pllxc_ops = { .is_enabled = clk_pll_is_enabled, - .enable = clk_pll_iddq_enable, - .disable = clk_pll_iddq_disable, + .enable = clk_pll_enable, + .disable = clk_pll_disable, .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, @@ -1527,8 +1498,8 @@ static const struct clk_ops tegra_clk_pllxc_ops = { static const struct clk_ops tegra_clk_pllm_ops = { .is_enabled = clk_pll_is_enabled, - .enable = clk_pll_iddq_enable, - .disable = clk_pll_iddq_disable, + .enable = clk_pll_enable, + .disable = clk_pll_disable, .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllm_set_rate, @@ -1545,8 +1516,8 @@ static const struct clk_ops tegra_clk_pllc_ops = { static const struct clk_ops tegra_clk_pllre_ops = { .is_enabled = clk_pll_is_enabled, - .enable = clk_pll_iddq_enable, - .disable = clk_pll_iddq_disable, + .enable = clk_pll_enable, + .disable = clk_pll_disable, .recalc_rate = clk_pllre_recalc_rate, .round_rate = clk_pllre_round_rate, .set_rate = clk_pllre_set_rate, @@ -1815,8 +1786,8 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) static const struct clk_ops tegra_clk_pllss_ops = { .is_enabled = clk_pll_is_enabled, - .enable = clk_pll_iddq_enable, - .disable = clk_pll_iddq_disable, + .enable = clk_pll_enable, + .disable = clk_pll_disable, .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/