Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946142AbbDXQv4 (ORCPT ); Fri, 24 Apr 2015 12:51:56 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1068 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966591AbbDXQsw (ORCPT ); Fri, 24 Apr 2015 12:48:52 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 24 Apr 2015 09:47:40 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Date: Fri, 24 Apr 2015 12:47:51 -0400 Message-ID: <1429894079-25052-12-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1429894079-25052-1-git-send-email-rklein@nvidia.com> References: <1429894079-25052-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1851 Lines: 62 From: Bill Huang If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths._ Signed-off-by: Bill Huang --- drivers/clk/tegra/clk-pll.c | 12 ++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index f612a8b65651..5677a5cdd3f7 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -355,6 +355,12 @@ static int clk_pll_enable(struct clk_hw *hw) udelay(2); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val &= ~BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); @@ -376,6 +382,12 @@ static void clk_pll_disable(struct clk_hw *hw) _clk_pll_disable(hw); + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val |= BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + if (pll->params->iddq_reg) { val = pll_readl(pll->params->iddq_reg, pll); val |= BIT(pll->params->iddq_bit_idx); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index b009c803f277..142999f1cd24 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -217,6 +217,8 @@ struct tegra_clk_pll_params { u32 lock_enable_bit_idx; u32 iddq_reg; u32 iddq_bit_idx; + u32 reset_reg; + u32 reset_bit_idx; u32 sdm_din_reg; u32 sdm_din_mask; u32 sdm_ctrl_reg; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/