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Date: Tue, 31 Oct 2000 16:18:10 -0700
From: "Jeff V. Merkey" <jmerkey@timpanogas.org>
Organization: TRG, Inc.
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To: mingo@elte.hu
CC: Pavel Machek <pavel@suse.cz>,
        "Jeff V. Merkey" <jmerkey@vger.timpanogas.org>,
        linux-kernel@vger.kernel.org
Subject: Re: 2.2.18Pre Lan Performance Rocks!
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Ingo Molnar wrote:
> 
> On Tue, 31 Oct 2000, Jeff V. Merkey wrote:
> 
> > [...] These types of optimizations are possible when people have
> > acccess to Intel Red Cover documents, [...]
> 
> optimizing away AGIs has been documented by public Intel PDFs for years:
> 
>  [...] Since the Pentium processor has two integer pipelines, a register
>  used as the base or index component of an effective address calculation
>  (in either pipe) causes an additional clock cycle if that register is the
>  destination of either instruction from the immediately preceding clock
>  cycle. This effect is known as Address Generation Interlock (AGI).
> 
> (ditto for the p6 core CPUs), and GCC (IIRC) tries to avoid AGI conflicts
> as much as possible. (and this kind of stuff belongs into the compiler)

Odd.  When I profile Linux with EMON, I see tons of them.  Anywhere code
does

mov    eax, addr
mov    [addr], ebx

one will get generated.  Even something as simple as:

mov    eax, addr
inc    eax
dec    eax
mov    [addr]. ebx

will avoid an AGI (since the other pipeline has now been allowed a few
clocks to fetch the address and load it).

Jeff



> 
>         Ingo
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