Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964835AbbD0PVf (ORCPT ); Mon, 27 Apr 2015 11:21:35 -0400 Received: from mail-bl2on0105.outbound.protection.outlook.com ([65.55.169.105]:57984 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932482AbbD0PVc (ORCPT ); Mon, 27 Apr 2015 11:21:32 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; gmail.com; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NNH1BM-08-B6W-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , , , CC: , , , , , Subject: [PATCH] x86, amd: Set X86_FEATURE_EXTD_APICID for future processors Date: Mon, 27 Apr 2015 10:25:51 -0500 Message-ID: <1430148351-9013-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(428002)(199003)(189002)(77156002)(5001770100001)(77096005)(229853001)(46102003)(105586002)(575784001)(47776003)(86362001)(2201001)(36756003)(50226001)(87936001)(101416001)(19580405001)(50466002)(19580395003)(50986999)(48376002)(53416004)(92566002)(106466001)(62966003);DIR:OUT;SFP:1102;SCL:1;SRVR:BL2PR02MB531;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BL2PR02MB531; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006)(3002001);SRVR:BL2PR02MB531;BCL:0;PCL:0;RULEID:;SRVR:BL2PR02MB531; X-Forefront-PRVS: 0559FB9674 X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2015 15:21:26.8666 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR02MB531 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1805 Lines: 46 Decision to use a 4-bit mask or 8-bit mask in default_get_apic_id() is controlled by setting capability bit X86_FEATURE_EXTD_APICID. Currently, we detect extended APIC ID support by accessing Link Transaction Control register D18F0x68 in PCI config space. But, not even that is needed as we can safely postulate that future AMD processors will support 8-bit APIC IDs and we can simply set that feature bit on them, without the PCI access. Signed-off-by: Aravind Gopalakrishnan --- arch/x86/kernel/cpu/amd.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index fd470eb..20b6813 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -520,8 +520,16 @@ static void early_init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K6_MTRR); #endif #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) - /* check CPU config space for extended APIC ID */ - if (cpu_has_apic && c->x86 >= 0xf) { + /* + * ApicID can always be treated as a 8bit value for + * AMD APIC versions >= 0x10. So, we can safely set + * X86_FEATURE_EXTD_APICID unconditionally for + * families after 16h. + */ + if (cpu_has_apic && c->x86 > 0x16) { + set_cpu_cap(c, X86_FEATURE_EXTD_APICID); + } else if (cpu_has_apic && c->x86 >= 0xf) { + /* check CPU config space for extended APIC ID */ unsigned int val; val = read_pci_config(0, 24, 0, 0x68); if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/