Message-ID: <553E5FD8.2070709@redhat.com>
Date: Mon, 27 Apr 2015 18:12:08 +0200
From: Denys Vlasenko <dvlasenk@redhat.com>
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To: Linus Torvalds <torvalds@linux-foundation.org>,
        Borislav Petkov <bp@alien8.de>
CC: Andy Lutomirski <luto@amacapital.net>, Andy Lutomirski <luto@kernel.org>,
        X86 ML <x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
        Denys Vlasenko <vda.linux@googlemail.com>,
        Brian Gerst <brgerst@gmail.com>, Ingo Molnar <mingo@kernel.org>,
        Steven Rostedt <rostedt@goodmis.org>, Oleg Nesterov <oleg@redhat.com>,
        Frederic Weisbecker <fweisbec@gmail.com>,
        Alexei Starovoitov <ast@plumgrid.com>, Will Drewry <wad@chromium.org>,
        Kees Cook <keescook@chromium.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86_64, asm: Work around AMD SYSRET SS descriptor attribute
 issue
References: <5d120f358612d73fc909f5bfa47e7bd082db0af0.1429841474.git.luto@kernel.org>	<20150425211206.GE32099@pd.tnic>	<CALCETrWvqyCYOzCYXz7ZnzaM0obbidqo5CxVp2Hn1ELEiC3m3g@mail.gmail.com>	<20150427085305.GB6774@pd.tnic>	<20150427113506.GG6774@pd.tnic> <CA+55aFykNBrdHFSVeLftG7Ujx4Tk=MuUJXD2rNYn9kwL+kLN5w@mail.gmail.com>
In-Reply-To: <CA+55aFykNBrdHFSVeLftG7Ujx4Tk=MuUJXD2rNYn9kwL+kLN5w@mail.gmail.com>
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On 04/27/2015 04:57 PM, Linus Torvalds wrote:
> On Mon, Apr 27, 2015 at 4:35 AM, Borislav Petkov <bp@alien8.de> wrote:
>>
>>         /*
>>          * Change top 16 bits to be the sign-extension of 47th bit, if this
>>          * changed %rcx, it was not canonical.
>>          */
>>         ALTERNATIVE "", \
>>                 "shl    $(64 - (47+1)), %rcx; \
>>                  sar    $(64 - (47+1)), %rcx; \
>>                  cmpq   %rcx, %r11; \
>>                  jne    opportunistic_sysret_failed", X86_BUG_SYSRET_CANON_RCX
> 
> Guys, if we're looking at cycles for this, then don't do the "exact
> canonical test". and go back to just doing
> 
>         shr $__VIRTUAL_MASK_SHIFT, %rcx
>         jnz opportunistic_sysret_failed
> 
> which is much smaller.

It is smaller, but not by much. It is two instructions smaller.
On disassembly level, the changes are:

cmp %rcx,0x80(%rsp) -> mov 0x80(%rsp),%r11; cmp %rcx,%r11
shr $0x2f,%rcx      -> shl $0x10,%rcx; sar $0x10,%rcx; cmp %rcx,%r11
mov 0x58(%rsp),%rcx -> (eliminated)


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