Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965946AbbD1PHj (ORCPT ); Tue, 28 Apr 2015 11:07:39 -0400 Received: from mail-qk0-f180.google.com ([209.85.220.180]:34554 "EHLO mail-qk0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965617AbbD1PHg (ORCPT ); Tue, 28 Apr 2015 11:07:36 -0400 MIME-Version: 1.0 In-Reply-To: References: <1428490480-10144-1-git-send-email-tomeu.vizoso@collabora.com> <20150408115546.GA24271@red-moon> <552643E1.3060200@collabora.com> <285738930.THBQOWvsah@vostro.rjw.lan> <20150410100844.GC23730@red-moon> <20150417140819.GB2347@red-moon> From: Tomeu Vizoso Date: Tue, 28 Apr 2015 17:07:14 +0200 X-Google-Sender-Auth: brZlLjr-GjGX95tKE8TBP1KIYGQ Message-ID: Subject: Re: [PATCH] ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() To: Lorenzo Pieralisi Cc: "Rafael J. Wysocki" , "linux-tegra@vger.kernel.org" , "linux-pm@vger.kernel.org" , "Rafael J. Wysocki" , Russell King , Stephen Warren , Thierry Reding , Alexandre Courbot , Bartlomiej Zolnierkiewicz , Kyungmin Park , Daniel Lezcano , Kukjin Kim , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2177 Lines: 54 On 17 April 2015 at 17:02, Tomeu Vizoso wrote: > On 17 April 2015 at 16:08, Lorenzo Pieralisi wrote: >> On Thu, Apr 16, 2015 at 03:37:19PM +0100, Tomeu Vizoso wrote: >> >> [...] >> >>> >> I don't know what FIQs are. :-) >>> > >>> > In short, fast IRQs, it is a separate IRQ line handled as a separate >>> > exception source with some private (banked) registers that minimize registers >>> > saving/restoring. They are not identical to NMI on x86, since >>> > their behaviour (handling) may be overriden by platforms and they >>> > can be masked. >>> > >>> >> ->enter_freeze is entered with interrupts disabled on the local CPU. It is >>> >> not supposed to re-enable them. That is, while in the ->enter_freeze callback >>> >> routine, the CPU must not be interrupted aby anything other than NMI. >>> > >>> > It boils down to what FIQs handlers are allowed to do with tick frozen >>> > and what they are (may be) currently used for. >>> > >>> > Russell has more insights on this than I do, in particular what FIQs are >>> > currently used for on ARM and if we can leave them enabled safely with tick >>> > frozen. >>> >>> But even if it's currently safe to leave them enabled, is there any >>> reason for not disabling them? >> >> Ok, the point here is: either it is safe, and you leave them enabled, >> or it is not and we must disable them *before* enter_freeze() is entered. >> >> Disabling them in the platform enter_freeze() hook does not make sense, >> because this means we run with FIQs enabled with tick frozen, either >> it is safe or it is not, it can't be both. > > Sure, that's why I proposed doing it in arch_cpu_idle_enter/exit. > >> I would ask Russell opinion on this, before making any decision. > > Sure, that would be very welcome. Hi Russell, do you think FIQs should be disabled when the tick is frozen when going to suspend to idle? Thanks, Tomeu -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/