Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031603AbbD2ChT (ORCPT ); Tue, 28 Apr 2015 22:37:19 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:34521 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031333AbbD2ChP (ORCPT ); Tue, 28 Apr 2015 22:37:15 -0400 MIME-Version: 1.0 In-Reply-To: <20150428153813.GC11721@bshelton-desktop> References: <1428941550-4620-1-git-send-email-punnaia@xilinx.com> <858a607d-7c5a-4066-aa79-ab14c456b8e5@BN1BFFO11FD046.protection.gbl> <20150428153813.GC11721@bshelton-desktop> Date: Wed, 29 Apr 2015 08:07:14 +0530 X-Google-Sender-Auth: YehT4wbQq2RhIpY66c0mDVS5mL4 Message-ID: Subject: Re: [PATCH v6 1/3] nand: pl353: Add basic driver for arm pl353 smc nand interface From: punnaiah choudary kalluri To: Ben Shelton Cc: Punnaiah Choudary Kalluri , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , Kumar Gala , Rob Landley , "michal.simek@xilinx.com" , Grant Likely , "gregkh@linuxfoundation.org" , "jason@lakedaemon.net" , "ezequiel.garcia@free-electrons.com" , Arnd Bergmann , David Woodhouse , Brian Norris , "artem.bityutskiy@linux.intel.com" , "jussi.kivilinna@iki.fi" , Alexandre Courbot , "Khoronzhuk, Ivan" , "joern@logfs.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , Punnaiah Choudary Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2671 Lines: 72 On Tue, Apr 28, 2015 at 9:08 PM, Ben Shelton wrote: > Hi Punnaiah, > > On 04/13, Punnaiah Choudary Kalluri wrote: >> Add driver for arm pl353 static memory controller nand interface with >> HW ECC support. This controller is used in xilinx zynq soc for interfacing >> the nand flash memory. >> >> Signed-off-by: Punnaiah Choudary Kalluri > > [...] > >> + >> +static int pl353_nand_init_timing(struct device *dev, int mode) >> +{ >> + const struct nand_sdr_timings *time; >> + u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr; >> + ulong clkrate; >> + >> + time = onfi_async_timing_mode_to_sdr_timings(mode); >> + if (IS_ERR(time)) >> + return PTR_ERR(time); >> + >> + clkrate = pl353_smc_get_clkrate(dev); >> + t_rc = get_cyc_from_ns(clkrate, time->tRC_min / 1000); >> + t_wc = get_cyc_from_ns(clkrate, time->tWC_min / 1000); >> + t_rea = get_cyc_from_ns(clkrate, time->tREA_max / 1000); >> + t_wp = get_cyc_from_ns(clkrate, time->tWP_min / 1000); >> + t_clr = get_cyc_from_ns(clkrate, time->tCLR_min / 1000); >> + t_ar = get_cyc_from_ns(clkrate, time->tAR_min / 1000); >> + t_rr = get_cyc_from_ns(clkrate, time->tRR_min / 1000); > > I tested this patch set in conjunction with your PL353 SMC patch set. > > Our first stage bootloader sets the SMC memclk rate to 166.6 MHz, which leads > this code to calculate a t_rc and t_wc of 17 cycles for ONFI mode 0. As I > mentioned in my response to your SMC patch, this overflows the 4-bit-wide > register fields in the SMC that hold these values. The better way is fixing the frequency to correct value to avoid the overflow conditions. Even as per ONFI spec, the maximum cycle time for SDR mode is 20 ns and DDR mode is 10 ns. As you pointed i will update the smc driver with required boundary checks for the lower and upper limits. > > Could we somehow set it up so the NAND and SMC drivers work together to adjust > the memclk rate, if necessary, to achieve the desired timings? Or is there a > better way to handle this? Let me check on this. I didn't see the option to control the clock rate at module level, otherwise probably we can have DT entry and configure the required frequency during the probe time. Regards, Punnaiah > >> + >> + pl353_smc_set_cycles(dev, t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr); >> + >> + return 0; >> +} > > Thanks, > Ben -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/