Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031319AbbD2Gmo (ORCPT ); Wed, 29 Apr 2015 02:42:44 -0400 Received: from mga03.intel.com ([134.134.136.65]:6179 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752650AbbD2Gmm (ORCPT ); Wed, 29 Apr 2015 02:42:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,669,1422950400"; d="scan'208";a="720884318" Message-ID: <55407D5F.20207@linux.intel.com> Date: Wed, 29 Apr 2015 09:42:39 +0300 From: Jarkko Nikula User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.6.0 MIME-Version: 1.0 To: Lee Jones , Mika Westerberg CC: Andy Shevchenko , "Rafael J. Wysocki" , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Heikki Krogerus Subject: Re: [PATCH v1 3/3] mfd: Add support for Intel Sunrisepoint LPSS devices References: <1427803182-62543-1-git-send-email-andriy.shevchenko@linux.intel.com> <1427803182-62543-4-git-send-email-andriy.shevchenko@linux.intel.com> <20150428133259.GD9169@x1> <20150428134833.GJ1534@lahna.fi.intel.com> <20150428175735.GG9169@x1> In-Reply-To: <20150428175735.GG9169@x1> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1758 Lines: 39 Hi On 04/28/2015 08:57 PM, Lee Jones wrote: > On Tue, 28 Apr 2015, Mika Westerberg wrote: >> On Tue, Apr 28, 2015 at 02:32:59PM +0100, Lee Jones wrote: >>> I'm not convinced it's really an MFD. What does this hardware look >>> like? Are the Designware devices really in the same memory/register >>> space as the LPSS registers? >> >> Yes they are - there is only single MMIO BAR per PCI device holding, the >> host controller, iDMA and convergence layer registers. > > Are there publicly available docs? > https://download.01.org/future-platform-configuration-hub/skylake/register-definitions/332219_001_Final.pdf For instance UART Memory Mapped Registers (Chapter 1.2) starts from UART MMIO BAR + offset 0 (LPSS_DEV_OFFSET in the patch), UART Additional Registers (Ch 1.3) from offset 0x200 (LPSS_PRIV_OFFSET) and UART DMA Controller Register (Ch 1.4) from offset 0x800 (LPSS_IDMA_OFFSET). Idea here is that MFD layer here takes case of reset and clock control as well as register the host controllers and integrated DMAs as platform devices (not all have the iDMA and thus conditional registering of it using the intel_lpss_has_idma()). That allow us to keep this MFD part, host controller drivers and drivers/dma/dw/ changes independent from each other. Fox example host controller driver can detect the iDMA by checking is there a "lpss_priv" resource and set the slave DMA parameters and DMA filter function accordingly (which picks the channel only from associated iDMA device). -- Jarkko -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/