Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422752AbbD2JIh (ORCPT ); Wed, 29 Apr 2015 05:08:37 -0400 Received: from mga02.intel.com ([134.134.136.20]:43878 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031729AbbD2JIc (ORCPT ); Wed, 29 Apr 2015 05:08:32 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,670,1422950400"; d="scan'208";a="687327192" Date: Wed, 29 Apr 2015 12:08:26 +0300 From: Mika Westerberg To: Lee Jones Cc: Andy Shevchenko , "Rafael J. Wysocki" , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Heikki Krogerus , Jarkko Nikula Subject: Re: [PATCH v1 3/3] mfd: Add support for Intel Sunrisepoint LPSS devices Message-ID: <20150429090826.GM1534@lahna.fi.intel.com> References: <1427803182-62543-1-git-send-email-andriy.shevchenko@linux.intel.com> <1427803182-62543-4-git-send-email-andriy.shevchenko@linux.intel.com> <20150428133259.GD9169@x1> <20150428134833.GJ1534@lahna.fi.intel.com> <20150428175735.GG9169@x1> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150428175735.GG9169@x1> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1418 Lines: 31 On Tue, Apr 28, 2015 at 06:57:35PM +0100, Lee Jones wrote: > On Tue, 28 Apr 2015, Mika Westerberg wrote: > > On Tue, Apr 28, 2015 at 02:32:59PM +0100, Lee Jones wrote: > > > On Tue, 31 Mar 2015, Andy Shevchenko wrote: > > > > > > > The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH. > > > > The main difference to the previous platforms is that the LPSS devices are > > > > compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are > > > > present. > > > > > > > > This patch brings the driver for such devices found on Sunrisepoint PCH. > > > > > > I'm not convinced it's really an MFD. What does this hardware look > > > like? Are the Designware devices really in the same memory/register > > > space as the LPSS registers? > > > > Yes they are - there is only single MMIO BAR per PCI device holding, the > > host controller, iDMA and convergence layer registers. > > Are there publicly available docs? Yes, there is temporary spec here: https://download.01.org/future-platform-configuration-hub/skylake/register-definitions/332219_001_Final.pdf (it will be part of the PCH public documentation, once it is released). -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/