Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751054AbbD3NSQ (ORCPT ); Thu, 30 Apr 2015 09:18:16 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52769 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750766AbbD3NSP (ORCPT ); Thu, 30 Apr 2015 09:18:15 -0400 Message-Id: <1430399894.517718.260752813.340456D5@webmail.messagingengine.com> X-Sasl-Enc: +qspwU+1SlwbTgkV191hy0FkMdN6mvFrtYQYbTl9z8rS 1430399894 From: Henrique de Moraes Holschuh To: Borislav Petkov , Alexander Hirsch <1zeeky@gmail.com> Cc: linux-kernel@vger.kernel.org, x86@kernel.org MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-Mailer: MessagingEngine.com Webmail Interface - ajax-e11d94ea Subject: Re: [PATCH] x86/microcode: Allow early loading without initrd Date: Thu, 30 Apr 2015 10:18:14 -0300 In-Reply-To: <20150426161609.GA4053@pd.tnic> References: <20150426170314.210e921c@netblarch.fritz.box> <20150426161609.GA4053@pd.tnic> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1802 Lines: 30 On Sun, Apr 26, 2015, at 13:16, Borislav Petkov wrote: > * the early loader was done with initrd in mind and it was/still is its > main source for microcode blobs early in the boot. So if we want to > make it not-mandatory, then the driver needs to be reorganized so that > builtin blobs and initrd blobs loading paths are cleanly untangled. The > ifdeffery thing might work now but is certainly not future-proof so it > would need to be designed in a cleaner way. > > Perhaps something like a microcode cache of patches the AMD loader has, > all decoupled from the loading paths or so... I don't have a good idea > right now. I'll have to think about it. Well, the *early* Intel driver does have a cache of sorts. It could use (a lot of) love, though... The "cache" in the early intel microcode update driver is implemented by mc_saved_in_initrd[]. It is currently sub-optimal, in that it has MAX_UCODE_COUNT slots (128 slots). The worst-case real-world fill of this cache is, currently, 7 slots (processor signature 0x6FB). The typical fill would be 1-4 slots. If we change the code to store at maximum one microcode per pfmask bit plus some other details to handle the "processor does not support pfmask, so it is all zeroes" special case, we can safely change MAX_UCODE_COUNT to either 8 or 9, depending on implementation details. -- "One disk to rule them all, One disk to find them. One disk to bring them all and in the darkness grind them. In the Land of Redmond where the shadows lie." -- The Silicon Valley Tarot Henrique Holschuh -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/