Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753093AbbD3Tw1 (ORCPT ); Thu, 30 Apr 2015 15:52:27 -0400 Received: from mail-bn1on0137.outbound.protection.outlook.com ([157.56.110.137]:7584 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750802AbbD3TwY (ORCPT ); Thu, 30 Apr 2015 15:52:24 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NNMXV4-07-1WS-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 0/4] Enable deferred error interrupts Date: Thu, 30 Apr 2015 09:49:21 -0500 Message-ID: <1430405365-4473-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(106466001)(5001770100001)(50986999)(48376002)(229853001)(86362001)(46102003)(101416001)(53416004)(50466002)(36756003)(105586002)(87936001)(50226001)(62966003)(77156002)(92566002)(77096005)(47776003)(2201001);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR02MB1112;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1112;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1240; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN3PR02MB1112;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1112; X-Forefront-PRVS: 056297E276 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2015 19:52:19.5583 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR02MB1112 X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1794 Lines: 42 Newer AMD processors can generate deferred errors and can be configured to generate APIC interrupts on such events. This patchset introduces a new interrupt handler for deferred errors and configures the HW if the feature is present. Patch1: Defines SUCCOR cpuid bit. This indicates prescence of features such as data poisoning and deferred error interrupts in hardware. Patch2: Implement the interrupt handler. - setup vector number, build the interrupt and implement handler function in this patch. Patch3, Patch 4: Cleanups in the code. No functional changes are introduced. Aravind Gopalakrishnan (4): x86/mce: Define 'SUCCOR' cpuid bit x86/mce/amd: Introduce deferred error interrupt handler x86, irq: Cleanup ordering of vector numbers x86/mce/amd: Rename setup_APIC_mce arch/x86/include/asm/entry_arch.h | 3 + arch/x86/include/asm/hardirq.h | 3 + arch/x86/include/asm/hw_irq.h | 2 + arch/x86/include/asm/irq_vectors.h | 11 ++-- arch/x86/include/asm/mce.h | 6 +- arch/x86/include/asm/trace/irq_vectors.h | 6 ++ arch/x86/include/asm/traps.h | 3 +- arch/x86/kernel/cpu/mcheck/mce.c | 1 + arch/x86/kernel/cpu/mcheck/mce_amd.c | 105 ++++++++++++++++++++++++++++++- arch/x86/kernel/entry_64.S | 5 ++ arch/x86/kernel/irq.c | 6 ++ arch/x86/kernel/irqinit.c | 4 ++ arch/x86/kernel/traps.c | 4 ++ 13 files changed, 150 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/