Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752764AbbD3RrM (ORCPT ); Thu, 30 Apr 2015 13:47:12 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:38405 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752620AbbD3RqJ (ORCPT ); Thu, 30 Apr 2015 13:46:09 -0400 From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Mike Turquette , Stephen Boyd , Jean-Francois Moine , Michael Welling , Russell King , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clk: si5351: Reset PLL after rate change Date: Thu, 30 Apr 2015 19:45:54 +0200 Message-Id: <1430415954-29517-5-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1430415954-29517-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1430415954-29517-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2405 Lines: 73 When changing PLL rate significantly, PLLs have to be reset. Add a function to perform and check for successful PLL reset. Signed-off-by: Sebastian Hesselbarth --- Cc: Mike Turquette Cc: Stephen Boyd Cc: Jean-Francois Moine Cc: Michael Welling Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/clk-si5351.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index beeb57bbb04c..9b97c134e3c1 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -366,6 +366,32 @@ static const struct clk_ops si5351_vxco_ops = { * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3) * */ +static int si5351_pll_reset(struct si5351_hw_data *hwdata) +{ + unsigned long timeout; + u8 mask = (hwdata->num == 0) ? + SI5351_STATUS_LOL_A : SI5351_STATUS_LOL_B; + + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + (hwdata->num == 0) ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); + timeout = jiffies + msecs_to_jiffies(100); + do { + if ((si5351_reg_read(hwdata->drvdata, SI5351_DEVICE_STATUS) & + mask) == 0) + break; + if (time_after(jiffies, timeout)) { + dev_err(&hwdata->drvdata->client->dev, + "timeout waiting for pll %d reset\n", + hwdata->num); + return -EBUSY; + }; + udelay(250); + } while (true); + + return 0; +} + static int _si5351_pll_reparent(struct si5351_driver_data *drvdata, int num, enum si5351_pll_src parent) { @@ -519,6 +545,9 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, SI5351_CLK_INTEGER_MODE, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); + /* reset pll after rate change */ + si5351_pll_reset(hwdata); + dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", __func__, __clk_get_name(hwdata->hw.clk), -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/