Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752359AbbD3U5f (ORCPT ); Thu, 30 Apr 2015 16:57:35 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3518 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750852AbbD3U5c (ORCPT ); Thu, 30 Apr 2015 16:57:32 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 30 Apr 2015 13:56:17 -0700 Message-ID: <5542973A.5000402@nvidia.com> Date: Thu, 30 Apr 2015 16:57:30 -0400 From: Rhyland Klein User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Andrew Bresticker CC: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 19/19] clk: tegra210: add support for Tegra210 clocks References: <1430328109-537-1-git-send-email-rklein@nvidia.com> <1430328109-537-20-git-send-email-rklein@nvidia.com> In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3078 Lines: 79 On 4/30/2015 4:43 PM, Andrew Bresticker wrote: > Hi Rhyland, > > On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein wrote: >> Implement clock support for Tegra210. >> >> Signed-off-by: Rhyland Klein > >> --- /dev/null >> +++ b/drivers/clk/tegra/clk-tegra210.c > >> + /* PLLU */ >> + val = readl(clk_base + pll_u_params.base_reg); >> + val &= ~BIT(24); /* disable PLLU_OVERRIDE */ >> + writel(val, clk_base + pll_u_params.base_reg); >> + >> + clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, >> + &pll_u_params, &pll_u_lock); >> + clk_register_clkdev(clk, "pll_u", NULL); >> + clks[TEGRA210_CLK_PLL_U] = clk; >> + >> + tegra210_utmi_param_configure(clk_base); >> + >> + /* PLLU_480M */ >> + clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", >> + CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, >> + 22, 0, &pll_u_lock); >> + clk_register_clkdev(clk, "pll_u_480M", NULL); >> + clks[TEGRA210_CLK_PLL_U_480M] = clk; >> + >> + /* PLLU_60M */ >> + clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", >> + CLK_SET_RATE_PARENT, 1, 8); >> + clk_register_clkdev(clk, "pll_u_60M", NULL); >> + clks[TEGRA210_CLK_PLL_U_60M] = clk; >> + >> + /* PLLU_48M */ >> + clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", >> + CLK_SET_RATE_PARENT, 1, 10); >> + clk_register_clkdev(clk, "pll_u_48M", NULL); >> + clks[TEGRA210_CLK_PLL_U_48M] = clk; >> + >> + /* PLLU_12M */ >> + clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", >> + CLK_SET_RATE_PARENT, 1, 40); >> + clk_register_clkdev(clk, "pll_u_12M", NULL); >> + clks[TEGRA210_CLK_PLL_U_12M] = clk; > > The PLLU hierarchy isn't quite right here. pll_u_480M is derived from > the VCO output of pll_u (480Mhz) rather than the final output > (240Mhz). It also looks, from downstream kernels and from the "PLLU > Configuration Information" table in the TRM, that pll_u_48M and > pll_u_60M are derived from pll_u_out1 and pll_u_out2, respectively. I > don't see any mention of a 12Mhz output (pll_u_12M) either. > > So I think the PLLU clock tree looks something like this: > > pll_u_vco (480Mhz) > pll_u_480M (480Mhz - gated by PLLU_BASE[22]) > pll_u (240Mhz) > pll_u_out1 (48Mhz - PLLU_OUTA[15:0]) > pll_u_48M (48Mhz - gated by PLLU_BASE[25]) > pll_u_out2 (60Mhz - PLLU_OUTA[31:16]) > pll_u_60M (60Mhz - gated by PLLU_BASE[23]) > > -Andrew > Thanks for pointing this out, I'll look into it for v3. -rhyland -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/