Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752381AbbEDQly (ORCPT ); Mon, 4 May 2015 12:41:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:3259 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751930AbbEDQjO (ORCPT ); Mon, 4 May 2015 12:39:14 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 04 May 2015 09:37:24 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Bill Huang Subject: [PATCH v4 14/20] clk: tegra: pll: Adjust vco_min if SDM present Date: Mon, 4 May 2015 12:37:34 -0400 Message-ID: <1430757460-9478-15-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1430757460-9478-1-git-send-email-rklein@nvidia.com> References: <1430757460-9478-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4581 Lines: 125 From: Bill Huang This code makes use of the SDM fractional divider if present to contrain the allowable programming range of the PLL divider register bitfields to take advantage of higher frequency granularity that can be induced by the SDM divider. Based on original work by Aleksandr Frid Signed-off-by: Bill Huang --- drivers/clk/tegra/clk-pll.c | 29 ++++++++++++++++++++++++++++- drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index b16263e978d7..94416018e35c 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1635,7 +1635,6 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = { .recalc_rate = clk_pll_recalc_rate, }; - struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, @@ -1662,6 +1661,10 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); if (err) return ERR_PTR(err); @@ -1700,6 +1703,10 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); @@ -1756,6 +1763,10 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLLM; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); @@ -2186,6 +2197,10 @@ struct clk *tegra_clk_register_pllc_tegra210(const char *name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + pll_params->flags |= TEGRA_PLL_BYPASS; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll)) @@ -2224,6 +2239,10 @@ struct clk *tegra_clk_register_pllxc_tegra210(const char *name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); @@ -2271,6 +2290,10 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + /* initialize PLL to minimum rate */ cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); @@ -2335,6 +2358,10 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + if (pll_params->adjust_vco) + pll_params->vco_min = pll_params->adjust_vco(pll_params, + parent_rate); + pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLLMB; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 4644f43ca100..fb4caa510583 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -248,6 +248,8 @@ struct tegra_clk_pll_params { int (*calc_rate)(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate); + unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, + unsigned long parent_rate); }; #define TEGRA_PLL_USE_LOCK BIT(0) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/