Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751950AbbEDSrD (ORCPT ); Mon, 4 May 2015 14:47:03 -0400 Received: from mail.skyhub.de ([78.46.96.112]:44763 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751015AbbEDSq4 (ORCPT ); Mon, 4 May 2015 14:46:56 -0400 Date: Mon, 4 May 2015 20:46:43 +0200 From: Borislav Petkov To: Aravind Gopalakrishnan Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, tony.luck@intel.com, jiang.liu@linux.intel.com, yinghai@kernel.org, x86@kernel.org, dvlasenk@redhat.com, JBeulich@suse.com, slaoub@gmail.com, luto@amacapital.net, dave.hansen@linux.intel.com, oleg@redhat.com, rostedt@goodmis.org, rusty@rustcorp.com.au, prarit@redhat.com, linux@rasmusvillemoes.dk, jroedel@suse.de, andriy.shevchenko@linux.intel.com, macro@linux-mips.org, wangnan0@huawei.com, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, Robert Richter Subject: Re: [PATCH 2/4] x86/mce/amd: Introduce deferred error interrupt handler Message-ID: <20150504184643.GH3829@pd.tnic> References: <1430405365-4473-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1430405365-4473-3-git-send-email-Aravind.Gopalakrishnan@amd.com> <20150503092212.GC18048@pd.tnic> <5547906E.3060701@amd.com> <20150504154652.GF3829@pd.tnic> <5547A780.8080800@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <5547A780.8080800@amd.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2003 Lines: 56 On Mon, May 04, 2015 at 12:08:16PM -0500, Aravind Gopalakrishnan wrote: > Not sure if lvt_off_valid() can be reused for deferred error interrupt > setup. It expects some some of info to be in struct threshold_block > which is fine for threshold errors and the shifts for offset are > different too. I meant that thresholding and IBS is being taken care of by that function. > For deferred errors, the workaround is a little different as it > applies to only the given family/model right now. If the workaround > needs to be applied for future processors, we can extend the family > check for those right? Or, you can do the check for all families as we're behind a CPUID bit anyway. This is why CPUID bits are a good thing :-) > If we setup 'm.addr' in amd_threshold_interrupt() and > amd_deferred_error_interrupt() properly, then amd_decode_mce() would > actually have some value in m->addr to report. > > I didn't mean to say HW doesn't provide us the information in the addr > and/or the misc registers. So you can use mce_read_aux(), yeah, you can move it to mce-internal.h > The addr, misc registers are still valid for threshold, deferred errors. > (Of course, misc is valid only if m->status & MCI_STATUS_MISCV) > > My point was, in __log_error(), we can read relevant status and addr MSRs to > be passed to mce_log() as those are the only pieces of information we use in > the decoding chain; and discard the m.misc assignment we do for threshold > errors. But MCx_MISC is important for thresholding errors, it carries the ErrCnt and stuff. So you can pass a parameter to __log_error(..., threshold=true, misc) and do if (threshold) m.misc = misc; Right? -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/