Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751913AbbEDTHF (ORCPT ); Mon, 4 May 2015 15:07:05 -0400 Received: from mail-bn1on0112.outbound.protection.outlook.com ([157.56.110.112]:24573 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750932AbbEDTHA (ORCPT ); Mon, 4 May 2015 15:07:00 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NNUAF8-07-GMO-02 X-M-MSG: Message-ID: <5547C343.2020507@amd.com> Date: Mon, 4 May 2015 14:06:43 -0500 From: Aravind Gopalakrishnan User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Borislav Petkov CC: , , , , , , , , , , , , , , , , , , , , , , , Robert Richter Subject: Re: [PATCH 2/4] x86/mce/amd: Introduce deferred error interrupt handler References: <1430405365-4473-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1430405365-4473-3-git-send-email-Aravind.Gopalakrishnan@amd.com> <20150503092212.GC18048@pd.tnic> <5547906E.3060701@amd.com> <20150504154652.GF3829@pd.tnic> <5547A780.8080800@amd.com> <20150504184643.GH3829@pd.tnic> In-Reply-To: <20150504184643.GH3829@pd.tnic> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(51694002)(51704005)(479174004)(164054003)(377454003)(189002)(24454002)(199003)(65816999)(105586002)(23676002)(120886001)(59896002)(2950100001)(36756003)(80316001)(83506001)(64126003)(50466002)(46102003)(87936001)(4001350100001)(93886004)(92566002)(33656002)(86362001)(47776003)(106466001)(77096005)(110136002)(54356999)(62966003)(50986999)(87266999)(77156002)(76176999)(101416001);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR02MB074;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR02MB074;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR02MB473; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BY2PR02MB074;BCL:0;PCL:0;RULEID:;SRVR:BY2PR02MB074; X-Forefront-PRVS: 05669A7924 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2015 19:06:48.1087 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR02MB074 X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2048 Lines: 55 On 5/4/2015 1:46 PM, Borislav Petkov wrote: >> For deferred errors, the workaround is a little different as it >> applies to only the given family/model right now. If the workaround >> needs to be applied for future processors, we can extend the family >> check for those right? > Or, you can do the check for all families as we're behind a CPUID bit > anyway. This is why CPUID bits are a good thing :-) Yep. Ok, Will do that. >> If we setup 'm.addr' in amd_threshold_interrupt() and >> amd_deferred_error_interrupt() properly, then amd_decode_mce() would >> actually have some value in m->addr to report. >> >> I didn't mean to say HW doesn't provide us the information in the addr >> and/or the misc registers. > So you can use mce_read_aux(), yeah, you can move it to mce-internal.h Ok, will do. Is it ok to grow another patch in a V2 for this instead of fixing it in this patch since it's a real bug? That should be helpful when someone wants to look up git logs of why this was done.. >> The addr, misc registers are still valid for threshold, deferred errors. >> (Of course, misc is valid only if m->status & MCI_STATUS_MISCV) >> >> My point was, in __log_error(), we can read relevant status and addr MSRs to >> be passed to mce_log() as those are the only pieces of information we use in >> the decoding chain; and discard the m.misc assignment we do for threshold >> errors. > But MCx_MISC is important for thresholding errors, it carries the ErrCnt > and stuff. > > So you can pass a parameter to __log_error(..., threshold=true, misc) > and do > > if (threshold) > m.misc = misc; > > Right? > Yeah, just wanted to keep __log_error() as generic as possible and not special case for threshold. But ok, since MCx_MISC is needed, I'll work it up as you suggested. Thanks, -Aravind. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/