Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752090AbbEDXeL (ORCPT ); Mon, 4 May 2015 19:34:11 -0400 Received: from mail-ig0-f175.google.com ([209.85.213.175]:32815 "EHLO mail-ig0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751642AbbEDXeE (ORCPT ); Mon, 4 May 2015 19:34:04 -0400 MIME-Version: 1.0 In-Reply-To: <1430757460-9478-11-git-send-email-rklein@nvidia.com> References: <1430757460-9478-1-git-send-email-rklein@nvidia.com> <1430757460-9478-11-git-send-email-rklein@nvidia.com> Date: Mon, 4 May 2015 16:34:03 -0700 X-Google-Sender-Auth: x4gaGYKjA1Bot-JN3Zk26I0Czbk Message-ID: Subject: Re: [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 From: Benson Leung To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2053 Lines: 54 On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein wrote: > For Tegra210, the logic to calculate out-of-table rates is different > from previous generations. Add callbacks that can be overridden to > allow for different ways of calculating rates. Default to > _cal_rate when not specified. You should mention that you're adding a new flag and new members that may override mdiv as well. > > Based on original work by Aleksandr Frid > > Signed-off-by: Rhyland Klein > --- > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index 3f92f1ad3961..b63ef31a2d7a 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -199,6 +199,8 @@ struct div_nmp { > * base register. > * TEGRA_PLL_BYPASS - PLL has bypass bit > * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring > + * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv > + * it may be more accurate (especially if SDM present) > */ > struct tegra_clk_pll_params { > unsigned long input_min; > @@ -235,7 +237,13 @@ struct tegra_clk_pll_params { > struct div_nmp *div_nmp; > struct tegra_clk_pll_freq_table *freq_table; > unsigned long fixed_rate; > + bool vco_out; vco_out is unused and unrelated to this change? > + u16 mdiv_default; > + u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); > void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); > + int (*calc_rate)(struct clk_hw *hw, > + struct tegra_clk_pll_freq_table *cfg, > + unsigned long rate, unsigned long parent_rate); Add kerneldoc for new members. -- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/