Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2993640AbbEEQGK (ORCPT ); Tue, 5 May 2015 12:06:10 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7801 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2993145AbbEEOSP (ORCPT ); Tue, 5 May 2015 10:18:15 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 05 May 2015 07:16:21 -0700 From: Jon Hunter To: Laxman Dewangan , Greg Kroah-Hartman , Jiri Slaby CC: , , , Jon Hunter Subject: [PATCH 2/8] serial: tegra: Add delay after enabling FIFO mode Date: Tue, 5 May 2015 15:17:53 +0100 Message-ID: <1430835479-6613-3-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430835479-6613-1-git-send-email-jonathanh@nvidia.com> References: <1430835479-6613-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1399 Lines: 38 For all tegra devices (up to t210), there is a hardware issue that requires software to wait for 3 UART clock periods after enabling the TX fifo, otherwise data could be lost. Signed-off-by: Jon Hunter --- drivers/tty/serial/serial-tegra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 9e08d3f07509..0d9d7ceb1dbb 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -885,6 +885,16 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); + /* Dummy read to ensure the write is posted */ + tegra_uart_read(tup, UART_SCR); + + /* + * For all tegra devices (up to t210), there is a hardware issue that + * requires software to wait for 3 UART clock periods after enabling + * the TX fifo, otherwise data could be lost. + */ + tegra_uart_wait_cycle_time(tup, 3); + /* * Initialize the UART with default configuration * (115200, N, 8, 1) so that the receive DMA buffer may be -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/