Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751733AbbEEWJR (ORCPT ); Tue, 5 May 2015 18:09:17 -0400 Received: from mail-ie0-f176.google.com ([209.85.223.176]:36132 "EHLO mail-ie0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751306AbbEEWJO (ORCPT ); Tue, 5 May 2015 18:09:14 -0400 Date: Tue, 5 May 2015 17:09:04 -0500 From: Bjorn Helgaas To: Gabriel FERNANDEZ Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , " David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , m-karicheri2@ti.com, Sachin Kamat , Andrew Lunn , Liviu Dudau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones , Gabriel Fernandez Subject: Re: [PATCH v3 2/5] PCI: st: Add Device Tree bindings for sti pcie Message-ID: <20150505220904.GD24643@google.com> References: <1428657168-12495-1-git-send-email-gabriel.fernandez@linaro.org> <1428657168-12495-3-git-send-email-gabriel.fernandez@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1428657168-12495-3-git-send-email-gabriel.fernandez@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3272 Lines: 80 On Fri, Apr 10, 2015 at 11:12:45AM +0200, Gabriel FERNANDEZ wrote: > sti pcie is built around a Synopsis Designware PCIe IP. > > Signed-off-by: Fabrice Gasnier > Signed-off-by: Gabriel Fernandez Arnd, Rob, can you ack this? > --- > Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt > new file mode 100644 > index 0000000..25fcab3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt > @@ -0,0 +1,53 @@ > +STMicroelectronics STi PCIe controller > + > +This PCIe host controller is based on the Synopsis Designware PCIe IP > +and thus inherits all the common properties defined in designware-pcie.txt. > + > +Required properties: > + - compatible: "st,stih407-pcie" > + - reg: base address and length of the pcie controller, mem-window address > + and length available to the controller. > + - interrupts: A list of interrupt outputs of the controller. Must contain an > + entry for each entry in the interrupt-names property. > + - interrupt-names: Should be "msi". STi interrupt that is asserted when an > + MSI is received. > + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg > + offset for IP configuration. > + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. > + Associated names must be "powerdown" and "softreset". > + - phys, phy-names: the phandle for the PHY device. > + Associated name must be "pcie" > + > +Optional properties: > + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. > + > +Example: > + > +pcie0: pcie@9b00000 { > + compatible = "st,pcie", "snps,dw-pcie"; > + device_type = "pci"; > + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ > + <0x2fff0000 0x00010000>, /* configuration space */ > + <0x40000000 0x80000000>; /* lmi mem window */ > + reg-names = "dbi", "config", "mem-window"; > + st,syscfg = <&syscfg_core 0xd8 0xe0>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ > + num-lanes = <1>; > + interrupts = ; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ > + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ > + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ > + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ > + > + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, > + <&softreset STIH407_PCIE0_SOFTRESET>; > + reset-names = "powerdown", > + "softreset"; > + phys = <&phy_port0 PHY_TYPE_PCIE>; > + phy-names = "pcie"; > +}; > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/