Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757036AbbEFBGN (ORCPT ); Tue, 5 May 2015 21:06:13 -0400 Received: from mail-qk0-f180.google.com ([209.85.220.180]:35037 "EHLO mail-qk0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752861AbbEFBGJ (ORCPT ); Tue, 5 May 2015 21:06:09 -0400 MIME-Version: 1.0 In-Reply-To: <20150505233534.GB18183@jhogan-linux.le.imgtec.org> References: <1428444258-25852-1-git-send-email-abrestic@chromium.org> <1428444258-25852-2-git-send-email-abrestic@chromium.org> <20150505220116.GE17687@jhogan-linux.le.imgtec.org> <20150505224352.GA18183@jhogan-linux.le.imgtec.org> <20150505233534.GB18183@jhogan-linux.le.imgtec.org> Date: Tue, 5 May 2015 18:06:08 -0700 X-Google-Sender-Auth: RjLD07mUAN8ru6w7ksSiUFKkKQw Message-ID: Subject: Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY From: Andrew Bresticker To: James Hogan Cc: Ralf Baechle , Kishon Vijay Abraham I , "devicetree@vger.kernel.org" , Linux-MIPS , "linux-kernel@vger.kernel.org" , James Hartley , Damien Horsley , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4058 Lines: 83 On Tue, May 5, 2015 at 4:35 PM, James Hogan wrote: > On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote: >> On Tue, May 5, 2015 at 3:43 PM, James Hogan wrote: >> > On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote: >> >> Hi James, >> >> >> >> On Tue, May 5, 2015 at 3:01 PM, James Hogan wrote: >> >> > Hi Andrew, >> >> > >> >> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote: >> >> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. >> >> >> >> >> >> Signed-off-by: Andrew Bresticker >> >> >> Cc: Rob Herring >> >> >> Cc: Pawel Moll >> >> >> Cc: Mark Rutland >> >> >> Cc: Ian Campbell >> >> >> Cc: Kumar Gala >> >> >> --- >> >> >> No changes from v1. >> >> >> --- >> >> >> .../devicetree/bindings/phy/pistachio-usb-phy.txt | 29 ++++++++++++++++++++++ >> >> >> include/dt-bindings/phy/phy-pistachio-usb.h | 16 ++++++++++++ >> >> >> 2 files changed, 45 insertions(+) >> >> >> create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt >> >> >> create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h >> >> >> >> >> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt >> >> >> new file mode 100644 >> >> >> index 0000000..afbc7e2 >> >> >> --- /dev/null >> >> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt >> >> >> @@ -0,0 +1,29 @@ >> >> >> +IMG Pistachio USB PHY >> >> >> +===================== >> >> >> + >> >> >> +Required properties: >> >> >> +-------------------- >> >> >> + - compatible: Must be "img,pistachio-usb-phy". >> >> >> + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. >> >> >> + - clocks: Must contain an entry for each entry in clock-names. >> >> >> + See ../clock/clock-bindings.txt for details. >> >> >> + - clock-names: Must include "usb_phy". >> >> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node. >> >> >> + - img,refclk: Indicates the reference clock source for the USB PHY. >> >> >> + See for a list of valid values. >> >> > >> >> > Possibly dumb question: why isn't the reference clock source specified >> >> > in the normal ways like the "usb_phy" clock is? >> >> > >> >> > Does the value required here depend on what usb_phy clock gets muxed >> >> > from or something? >> >> >> >> Right, the value indicates what clock "usb_phy" is: whether it comes >> >> from the core clock controller, the XO crystal, or is some external >> >> clock. It's a mux internal to the PHY. >> > >> > Okay. If its a software controllable mux, is there a particular reason >> > the DT doesn't describe it as such, i.e. have all 3 clock inputs, and >> > the driver somehow work out which to use? >> >> Well, I'm not sure how the driver would determine which clock to use >> without a device-tree property like the one I've got here :). Also, > > Does it make sense to just look for the "best" usable source clock based > on the supported rates listed in fsel_rate_map[] (for some definition of > "best" such as "fastest" / "slowest" / "first usable"), or are things > just not that simple? > > I'm just wondering how the DT writer would decide, since it seems to > come down to a policy decision rather than a description of the > hardware, which should probably be avoided in DT bindings if possible. Ah, sorry if that was unclear - this *is* describing a hardware property. The DT author would pick a value by looking at which clock is connected to the PHY in the schematic. -Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/