Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752272AbbEFQNt (ORCPT ); Wed, 6 May 2015 12:13:49 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14414 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751512AbbEFQNr (ORCPT ); Wed, 6 May 2015 12:13:47 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 06 May 2015 09:11:48 -0700 Message-ID: <554A3DB9.8080504@nvidia.com> Date: Wed, 6 May 2015 12:13:45 -0400 From: Rhyland Klein User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Thierry Reding , Benson Leung , Peter De Schrijver CC: Mike Turquette , Stephen Boyd , Stephen Warren , Alexandre Courbot , , , Subject: Re: [PATCH] clk: tegra: Update struct tegra_clk_pll_params kerneldoc References: <1430919815-22380-1-git-send-email-thierry.reding@gmail.com> In-Reply-To: <1430919815-22380-1-git-send-email-thierry.reding@gmail.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2361 Lines: 64 On 5/6/2015 9:43 AM, Thierry Reding wrote: > From: Thierry Reding > > Benson Leung pointed out that the kerneldoc for this structure has > become stale. Update the field descriptions to match the structure > content. > > Reported-by: Benson Leung > Signed-off-by: Thierry Reding > --- > drivers/clk/tegra/clk.h | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index f3782dedbdfb..c47e633616be 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -157,7 +157,7 @@ struct div_nmp { > }; > > /** > - * struct clk_pll_params - PLL parameters > + * struct tegra_clk_pll_params - PLL parameters > * > * @input_min: Minimum input frequency > * @input_max: Maximum input frequency > @@ -168,12 +168,22 @@ struct div_nmp { > * @base_reg: PLL base reg offset > * @misc_reg: PLL misc reg offset > * @lock_reg: PLL lock reg offset > - * @lock_bit_idx: Bit index for PLL lock status > + * @lock_mask: Bitmask for PLL lock status > * @lock_enable_bit_idx: Bit index to enable PLL lock > + * @iddq_reg: PLL IDDQ register offset > + * @iddq_bit_idx: Bit index to enable PLL IDDQ > + * @aux_reg: AUX register offset > + * @dyn_ramp_reg: Dynamic ramp control register offset > + * @ext_misc_reg: Miscellaneous control register offsets > + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) > + * @pmc_divp_reg: p divider PMC override register offset (PLLM) > + * @flags: PLL flags > + * @stepa_shift: Dynamic ramp step A field shift > + * @stepb_shift: Dynamic ramp step B field shift > * @lock_delay: Delay in us if PLL lock is not used > + * @div_nmp: offsets and widths on n, m and p fields > * @freq_table: array of frequencies supported by PLL > * @fixed_rate: PLL rate if it is fixed > - * @flags: PLL flags > * > * Flags: > * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for > Acked-by: Rhyland Klein -rhyland -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/