Message-ID: <554B7DAA.3040606@linux.intel.com>
Date: Thu, 07 May 2015 07:58:50 -0700
From: Dave Hansen <dave.hansen@linux.intel.com>
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To: Ingo Molnar <mingo@kernel.org>
CC: Ingo Molnar <mingo2.kernel.org@gmail.com>, linux-kernel@vger.kernel.org,
        Andy Lutomirski <luto@amacapital.net>, Borislav Petkov <bp@alien8.de>,
        Fenghua Yu <fenghua.yu@intel.com>, "H. Peter Anvin" <hpa@zytor.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Oleg Nesterov <oleg@redhat.com>, Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 084/208] x86/fpu: Rename xsave.header::xstate_bv to 'xfeatures'
References: <1430848300-27877-1-git-send-email-mingo@kernel.org> <1430848300-27877-6-git-send-email-mingo@kernel.org> <554904A6.8040503@linux.intel.com> <20150505181613.GA28562@gmail.com> <55490B1F.3080409@linux.intel.com> <20150506061603.GA13720@gmail.com> <554A5D23.2030405@linux.intel.com> <20150507122209.GB15656@gmail.com>
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On 05/07/2015 05:22 AM, Ingo Molnar wrote:
> I.e. are there any plans beyond using it strictly for full state 
> save/restore.

None that I know of, but having two (relatively) tiny features
(protection keys and MPX) might change things.

> Btw., regarding XCR0.PKRU: that enables 'Protection Keys' in the PTE 
> format. What's the main purpose of these keys? They seem to duplicate 
> the read/write bits in the PTE, with the exception that they don't 
> impact instruction fetches. So is this used to allow user-space to 
> execute but otherwise not read instructions?
> 
> Or some other purpose I missed?

You can change the permissions of a given key with writes to the
register without changing the PTE.  No TLB shootdown, plus the
permission changes are local to the CPU thread.

I have patches today if you're interested.

> In any case, these holes are really minor at the moment, and the 
> question is, what is the performance difference between a 'compactede' 
> XSAVE*/XRSTOR* pair, versus a standard format one?


Yeah, that would be interesting to know.

>>> Maybe once we get AVX512 in addition to MPX we can use compaction 
>>> materially: as there will be lots of tasks without MPX state but 
>>> with AVX512 state - in fact I suspect that will be the common 
>>> case.
>>
>> Right.
>>
>> But we'd need to get to a point where we are calling 'xsaves' with a 
>> Requested Feature BitMask (aka RFBM[]) that had holes in it.  As it 
>> stands today, we always call it with RFBM=-1 and so we always have 
>> XCOMP_BV = XCR0.
...
>> We'd need to determine which fields are in the init state before we 
>> do an xsaves.
> 
> Why? I don't think that's necessary.

"If RFBM[i] = 0, XSTATE_BV[i] is written as 0."

We need to pull XSTATE_BV in to the instruction mask when doing an
XSAVE* if our RFBM has bits unset that *are* set in XSTATE_BV.
Otherwise, we'll destroy the bits at XSAVE* time.

It's not a problem today because the instruction mask is always -1, so
it always has every bit set that *MIGHT* be set in XSTATE_BV.

As for the whole bit 63 thing...  It's possible and valid to have a
XCOMP_BV[62:0]=0 because the instruction mask only contained bits that
were unset in XCR0|IA32_XSS.  You need bit 63 to tell you which format
you are using.
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