Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752225AbbEGPTD (ORCPT ); Thu, 7 May 2015 11:19:03 -0400 Received: from mail-bn1bon0076.outbound.protection.outlook.com ([157.56.111.76]:50240 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751086AbbEGPRe (ORCPT ); Thu, 7 May 2015 11:17:34 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; codeaurora.org; dkim=none (message not signed) header.d=none; Authentication-Results: codeaurora.org; dkim=none (message not signed) header.d=none; From: To: , CC: , , , , , , , , "Dinh Nguyen" Subject: [PATCHv3 1/4] clk: socfpga: update clk.h so for Arria10 platform to use Date: Thu, 7 May 2015 10:12:00 -0500 Message-ID: <1431011523-10049-2-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1431011523-10049-1-git-send-email-dinguyen@opensource.altera.com> References: <1431011523-10049-1-git-send-email-dinguyen@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BN1PR02CA0026.namprd02.prod.outlook.com (10.141.56.26) To BN3PR03MB1366.namprd03.prod.outlook.com (25.163.34.152) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1366;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB152; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:;UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN3PR03MB1366;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1366;BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BLUPR03MB152;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB152; X-Forefront-PRVS: 056929CBB8 X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(6009001)(50986999)(48376002)(76176999)(229853001)(33646002)(189998001)(19580405001)(19580395003)(50226001)(50466002)(42186005)(53416004)(77096005)(47776003)(40100003)(66066001)(62966003)(77156002)(92566002)(122386002)(5001770100001)(5001960100002)(86362001)(5001920100001)(86152002)(107886002)(2950100001)(87976001)(46102003)(4001430100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR03MB1366;H:linux-builds1.altera.com;FPR:;SPF:None;MLV:sfv;LANG:en; X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1366 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BY2FFO11OLC015.protection.gbl X-Forefront-Antispam-Report: CIP:66.35.236.227;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(339900001)(189002)(199003)(50986999)(107886002)(5001960100002)(76176999)(77156002)(53416004)(50226001)(62966003)(77096005)(33646002)(105606002)(19580405001)(6806004)(5001770100001)(229853001)(19580395003)(40100003)(106466001)(87936001)(16796002)(2950100001)(122386002)(81156007)(46102003)(85426001)(86152002)(47776003)(50466002)(86362001)(48376002)(92566002)(66066001)(189998001)(7099028)(4001430100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUPR03MB152;H:sj-itexedge03.altera.priv.altera.com;FPR:;SPF:Fail;MLV:ovrnspm;MX:1;A:0;PTR:InfoDomainNonexistent;LANG:en; X-Forefront-PRVS: 056929CBB8 X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2015 15:17:30.3172 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.227];Helo=[sj-itexedge03.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB152 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1943 Lines: 58 From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 ---- drivers/clk/socfpga/clk.h | 6 +++++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..607ab35 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -32,14 +32,10 @@ #define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 -#define streq(a, b) (strcmp((a), (b)) == 0) - #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) { diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d291f60..b09a5d5 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -26,9 +26,13 @@ #define CLKMGR_L4SRC 0x70 #define CLKMGR_PERPLL_SRC 0xAC -#define SOCFPGA_MAX_PARENTS 3 +#define SOCFPGA_MAX_PARENTS 5 #define div_mask(width) ((1 << (width)) - 1) +#define streq(a, b) (strcmp((a), (b)) == 0) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + extern void __iomem *clk_mgr_base_addr; void __init socfpga_pll_init(struct device_node *node); -- 2.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/